參數(shù)資料
型號: EP7211-CP-A
廠商: CRYSTAL SEMICONDUCTOR CORP
元件分類: 外設(shè)及接口
英文描述: HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述: MULTIFUNCTION PERIPHERAL, PBGA256
封裝: PLASTIC, BGA-256
文件頁數(shù): 50/166頁
文件大?。?/td> 2623K
代理商: EP7211-CP-A
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
50
Functional Description
DS352PP3
JUL 2001
3.8
Serial Interfaces
The EP7211 offers the following serial interfaces in addition to the two UARTs.
The inputs/outputs of three of the serial synchronous interfaces (MCP, codec, and SSI2) are
multiplexed onto a single set of external interface pins. If the MCPSEL bit of SYSCON3 is low, then
either SSI2 or the codec interface will be selected to connect to the external pins. When Bit 0 of
SYSCON2 (SERSEL) is high, then the codec is connected to the external pins, when low the
master/slave SSI2 is connected to these pins. When the MCPSEL bit is set high, the MCP interface
is connected to the external pins. On power up, both the MCPSEL and SERSEL bits are reset low,
thus the master/slave SSI2 will be connected to these pins (and configured for slave mode operation
to avoid external drive clashes).
The following table contains pin definition information for the three multiplexed interfaces.
NOTE:
The internal names given to each of the three interfaces are unique to help differentiate them from
each other. The sections below that describe each of the three interfaces will use their respective
unique internal pin names for clarity.
*
p/u = use an 10 k pull-up
Table 3-12. Serial Interface Options
Type
Comments
Referred To As
Max. Transfer Speed
SPI/Microwire 1
Master mode only
ADC Interface
128 Kbps
SPI/Microwire 2
Master/slave mode
SSI2 Interface
512 Kbps
MCP Interface
Touchscreen, codecs, and GPIO
MCP Interface
9.216 Mbps
Codec Interface
Only
for use in the PLL clock mode
Codec Interface
64 Kbps
Table 3-13. Serial-Pin Assignments
Pin No.
LQFP
External
Pin Name
SSI2
Slave Mode
(Internal Name)
SSI2
Master Mode
Codec
Internal Name
MCP
Internal Name
Strength
63
SSICCLK
SSICCLK = serial
bit clock; Input
Output
PCMCLK =
Output
SIBCLK =
Output
1
65
SSITXFR
SSKTXFR = TX
frame sync; Input
Output
PCMSYNC =
Output
SIBSYNC =
Output
1
66
SSITXDA
SSITXDA = TX
data; Output
Output
PCMOUT =
Output
SIBDOUT =
Output
1
67
SSIRXDA
SSIRXDA = RX
data; Input
Input
PCMIN = Input
SIBDIN = Input
68
SSIRXFR
SSIRXFR = RX
frame sync; Input
Output
p/u*
p/u*
1
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