參數(shù)資料
型號： EP7211-CP-A
廠商： CRYSTAL SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述： MULTIFUNCTION PERIPHERAL, PBGA256
封裝： PLASTIC, BGA-256
文件頁數(shù)： 56/166頁
文件大小： 2623K
代理商： EP7211-CP-A
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
56
Functional Description
DS352PP3
JUL 2001
Figure 3-5. Audio Codec Enable Timing
Referring to the
Figure 3-5. Audio Codec Enable Timing
,
“
Ena
”
within the data frame on
SIBDOUT
represents a control register write to the codec to enable the input portion of the audio
codec. The register is updated with the write at the end of subframe 0, and the audio enable signal
within the codec goes high. Both the MCP and codec
’
s audio sample rate counters then start to
decrement on the next
SIBSYNC
pulse. In the example, a divisor value of 3 is used, causing the
counter to decrement to zero after 96 (32
x
3 = 96)
SIBCLK
cycles occur.
If the input portion of the audio codec is enabled when the counter reaches zero, a sample and A/D
conversion is made. The converted value is then placed into the correct field of the codec
’
s serial
shift register for transmission back to the MCP in the next data frame. If the output portion of the
audio codec is enabled, an audio data value is taken from the received data supplied by the MCP and
is used for a D/A conversion. Data used in the D/A conversion is always taken from the previous
MCP input frame. If no new data is available within the MCP
’
s audio transmit FIFO since the last
D/A conversion, the same data is used again (causing audio distortion).
Samples and conversions occur twice as shown in
Figure 3-5. Audio Codec Enable Timing
.
However, while the counter is decrementing for the third time, the CPU disables the audio codec by
issuing another control register write, represented by the
“
Dis
”
data frame on
SIBDOUT
. The
SIBSYNC
pulse following the write causes the disable to take effect, and the MCP and codec
’
s audio
sample rate counters are stopped and reset to their modulus value.
The MCP and the codec
’
s audio sample rate counters must be enabled coherently, so that
synchronization is achieved between the two. This is accomplished by first programming both the
MCP and codec
’
s sample rate modulus values, then performing a codec control register write to
enable the audio sampling rate counter within the codec. The MCP automatically decodes a write to
Subframe
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
SIBSYNC
SIBDOUT
Ena
Dis
Audio Ena
Counters
3
3
2
1
3
2
1
3
2
3...................3
Samp/Conv
相關(guān)PDF資料
PDF描述
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7309 HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP7211-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-D 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP7212 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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