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您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄19323 > EP2S30F672I4N (Altera)IC STRATIX II FPGA 30K 672-FBGA PDF資料下載

型號(hào)：	EP2S30F672I4N
廠商：	Altera
文件頁(yè)數(shù)：	351/768頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX II FPGA 30K 672-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	10
系列：	Stratix® II
LAB/CLB數(shù)：	1694
邏輯元件/單元數(shù)：	33880
RAM 位總計(jì)：	1369728
輸入/輸出數(shù)：	500
電源電壓：	1.15 V ~ 1.25 V
安裝類(lèi)型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	672-BBGA
供應(yīng)商設(shè)備封裝：	672-BGA（27x27）
其它名稱(chēng)：	544-1900 EP2S30F672I4N-ND

Altera Corporation

Stratix II Device Handbook, Volume 2

January 2008

Stratix II and Stratix II GX DDR Memory Support Overview

The DQS pins are listed in the Stratix II or Stratix II GX pin tables as

or DQS[17..0]B. The T denotes pins on the top of the

device and the B denotes pins on the bottom of the device. The

complement DQSn pins are marked as DQSn[17..0]T or

DQSn[17..0]B

. The corresponding DQ pins are marked as

DQ[17..0]T[3..0]

, where [17..0] indicates which DQS group the

pins belong to. Similarly, the corresponding DQVLD pins are marked as

DQVLD[8..0]T

, where [8..0] indicates which DQS group the pins

belong to. The numbering scheme starts from right to left on the package

bottom view. When not used as DQ, DQS, or DQSn pins, these pins are

available as regular I/O pins. Figure 3–7 shows the DQS pins in Stratix II

or Stratix II GX I/O banks.

The Quartus II software treats DQVLD pins as regular DQ pins.

Therefore, you must ensure that the DQVLD pin assigned in

your design corresponds to the pin table’s recommended

Figure 3–7. DQS Pins in Stratix II and Stratix II GX I/O Banks

Notes (1), (2), (3)

Notes to Figure 3–7:

There are up to 18 pairs of DQS and DQSn pins on both the top and bottom of the device. See Table 3–3 for the exact

number of DQS and DQSn pin pairs in each device package.

See Table 3–7 for the available DQS and DQSn pins in each mode and package.

Each DQS pin has a complement DQSn pin. DQS and DQSn pins are not differential.

The DQ pin numbering is based on ×4 mode. There are up to 8 DQS/DQ

groups in ×4 mode in I/O banks 3 and 8 and up to 10 DQS/DQ groups in

×4 mode in I/O banks 4 and 7. In ×8/×9 mode, two adjacent ×4 DQS/DQ

groups plus one parity pin are combined; one pair of DQS/DQSn pins

from the combined groups can drive all the DQ and parity pins. Since

there is an even number of DQS/DQ groups in an I/O bank, combining

groups is efficient. Similarly, in ×16/×18 mode, four adjacent ×4 DQS/DQ

groups plus two parity pins are combined and one pair of DQS/DQSn

pins from the combined groups can drive all the DQ and parity pins. In

Up to 8 Sets of

DQ & DQS Pins

Up to 10 Sets of

DQ & DQS Pins

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
EP2S-3G1	制造商:NEC 制造商全稱(chēng):NEC 功能描述:LOW SOUND PRESSURE
EP2S-3G1T	制造商:NEC 制造商全稱(chēng):NEC 功能描述:LOW SOUND PRESSURE
EP2S-3G1TT	制造商:NEC 制造商全稱(chēng):NEC 功能描述:LOW SOUND PRESSURE
EP2S-3G2	制造商:NEC 制造商全稱(chēng):NEC 功能描述:LOW SOUND PRESSURE
EP2S-3G2T	制造商:NEC 制造商全稱(chēng):NEC 功能描述:LOW SOUND PRESSURE

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