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型號(hào)：	EP2S30F672I4N
廠商：	Altera
文件頁(yè)數(shù)：	31/768頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX II FPGA 30K 672-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	10
系列：	Stratix® II
LAB/CLB數(shù)：	1694
邏輯元件/單元數(shù)：	33880
RAM 位總計(jì)：	1369728
輸入/輸出數(shù)：	500
電源電壓：	1.15 V ~ 1.25 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	672-BBGA
供應(yīng)商設(shè)備封裝：	672-BGA（27x27）
其它名稱：	544-1900 EP2S30F672I4N-ND

Altera Corporation

Stratix II Device Handbook, Volume 1

May 2007

IEEE Std. 1149.1 JTAG Boundary-Scan Support

Table 3–1. Stratix II JTAG Instructions

JTAG Instruction

Instruction Code

Description

SAMPLE/PRELOAD

00 0000 0101

Allows a snapshot of signals at the device pins to be captured and

examined during normal device operation, and permits an initial

data pattern to be output at the device pins. Also used by the

SignalTap II embedded logic analyzer.

00 0000 1111

Allows the external circuitry and board-level interconnects to be

tested by forcing a test pattern at the output pins and capturing test

results at the input pins.

11 1111 1111

Places the 1-bit bypass register between the TDI and TDO pins,

which allows the BST data to pass synchronously through selected

devices to adjacent devices during normal device operation.

00 0000 0111

Selects the 32-bit USERCODE register and places it between the

and TDO pins, allowing the USERCODE to be serially shifted

00 0000 0110

Selects the IDCODE register and places it between TDI and TDO,

allowing the IDCODE to be serially shifted out of TDO.

00 0000 1011

Places the 1-bit bypass register between the TDI and TDO pins,

which allows the BST data to pass synchronously through selected

devices to adjacent devices during normal device operation, while

tri-stating all of the I/O pins.

00 0000 1010

Places the 1-bit bypass register between the TDI and TDO pins,

which allows the BST data to pass synchronously through selected

devices to adjacent devices during normal device operation while

holding I/O pins to a state defined by the data in the boundary-scan

ICR instructions

Used when configuring a Stratix II device via the JTAG port with a

USB Blaster, MasterBlaster, ByteBlasterMV, or ByteBlaster II

download cable, or when using a .jam or .jbc via an embedded

processor or JRunner.

PULSE_NCONFIG

00 0000 0001

Emulates pulsing the nCONFIG pin low to trigger reconfiguration

even though the physical pin is unaffected.

00 0000 1101

Allows configuration of I/O standards through the JTAG chain for

JTAG testing. Can be executed before, during, or after

configuration. Stops configuration if executed during configuration.

Once issued, the CONFIG_IO instruction holds nSTATUS low to

reset the configuration device. nSTATUS is held low until the IOE

configuration register is loaded and the TAP controller state

machine transitions to the UPDATE_DR state.

SignalTap II

instructions

Monitors internal device operation with the SignalTap II embedded

logic analyzer.

Notes to Table 3–1:

Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.

For more information on using the CONFIG_IO instruction, see the MorphIO: An I/O Reconfiguration Solution for

Altera Devices White Paper.

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