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型號(hào)：	EP2S30F672I4N
廠商：	Altera
文件頁(yè)數(shù)：	199/768頁(yè)
文件大小：	0K
描述：	IC STRATIX II FPGA 30K 672-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	10
系列：	Stratix® II
LAB/CLB數(shù)：	1694
邏輯元件/單元數(shù)：	33880
RAM 位總計(jì)：	1369728
輸入/輸出數(shù)：	500
電源電壓：	1.15 V ~ 1.25 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	672-BBGA
供應(yīng)商設(shè)備封裝：	672-BGA（27x27）
其它名稱：	544-1900 EP2S30F672I4N-ND

Altera Corporation

Stratix II Device Handbook, Volume 2

July 2009

Enhanced PLLs

Single-ended or differential pins that can drive the fbin port for PLL 6.

Single-ended or differential pins that can drive the fbin port for PLL 11.

Single-ended or differential pins that can drive the fbin port for PLL 12.

Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do

not use this pin, connect it to ground.

PLL5_OUT[2..0]p/n

Single-ended or differential pins driven by C[5..0] ports from PLL 5.

PLL6_OUT[2..0]p/n

Single-ended or differential pins driven by C[5..0] ports from PLL 6.

PLL11_OUT[2..0]p/n

Single-ended or differential pins driven by C[5..0] ports from PLL 11.

PLL12_OUT[2..0]p/n

Single-ended or differential pins driven by C[5..0] ports from PLL 12.

Analog power for PLL 5. You must connect this pin to 1.2 V, even if the PLL is not

Analog ground for PLL 5. You can connect this pin to the GND plane on the board.

Analog power for PLL 6. You must connect this pin to 1.2 V, even if the PLL is not

Analog ground for PLL 6. You can connect this pin to the GND plane on the board.

Analog power for PLL 11. You must connect this pin to 1.2 V, even if the PLL is not

Analog ground for PLL 11. You can connect this pin to the GND plane on the

Analog power for PLL 12. You must connect this pin to 1.2 V, even if the PLL is not

Analog ground for PLL 12. You can connect this pin to the GND plane on the

Digital power for PLLs. You must connect this pin to 1.2 V, even if the PLL is not

VCC_PLL5_OUT

External clock output VCCIO power for PLL5_OUT0p, PLL5_OUT0n,

, PLL5_OUT1n, PLL5_OUT2p, and PLL5_OUT2n outputs from

VCC_PLL6_OUT

External clock output VCCIO power for PLL6_OUT0p, PLL6_OUT0n,

, PLL6_OUT1n and PLL6_OUT2p, PLL6_OUT2n outputs from

VCC_PLL11_OUT

External clock output VCCIO power for PLL11_OUT0p, PLL11_OUT0n,

, PLL11_OUT1n and PLL11_OUT2p, PLL11_OUT2n outputs

from PLL 11.

Table 1–7. Stratix II and Stratix II GX Enhanced PLL Pins (Part 2 of 3)

Description

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