參數(shù)資料
型號： DSP56303VL100
廠商： Freescale Semiconductor
文件頁數(shù)： 87/108頁
文件大?。?/td> 0K
描述： IC DSP 24BIT 100MHZ 196-MAPBGA
標準包裝： 126
系列： DSP563xx
類型： 定點
接口： 主機接口，SSI，SCI
時鐘速率： 100MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
DSP56303 Technical Data, Rev. 11
1-4
Freescale Semiconductor
Signals/Connections
1.3 Clock
1.4 PLL
1.5 External Memory Expansion Port (Port A)
Note:
When the DSP56303 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS.
1.5.1
External Address Bus
Table 1-4.
Clock Signals
Signal Name
Type
State During
Reset
Signal Description
EXTAL
Input
External Clock/Crystal Input—Interfaces the internal crystal oscillator input
to an external crystal or an external clock.
XTAL
Output
Chip-driven
Crystal Output—Connects the internal crystal oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
Table 1-5.
Phase-Locked Loop Signals
Signal Name
Type
State During
Reset
Signal Description
CLKOUT
Output
Chip-driven
Clock Output—Provides an output clock synchronized to the internal core
clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
PCAP
Input
PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to VCCP.
If the PLL is not used, PCAP can be tied to VCC, GND, or left floating.
PINIT
NMI
Input
PLL Initial—During assertion of RESET, the value of PINIT is written into the
PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether
the PLL is enabled or disabled.
Nonmaskable Interrupt—After RESET deassertion and during normal
instruction processing, this Schmitt-trigger input is the negative-edge-triggered
NMI request internally synchronized to CLKOUT.
Note: PINIT/NMI can tolerate 5 V.
Table 1-6.
External Address Bus Signals
Signal Name
Type
State During
Reset, Stop, or
Wait
Signal Description
A[0–17]
Output
Tri-stated
Address Bus—When the DSP is the bus master, A[0–17] are active-high outputs that
specify the address for external program and data memory accesses. Otherwise, the
signals are tri-stated. To minimize power dissipation, A[0–17] do not change state when
external memory spaces are not being accessed.
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