參數(shù)資料
型號(hào)： DSP56303VL100
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 2/108頁(yè)
文件大?。?/td> 0K
描述： IC DSP 24BIT 100MHZ 196-MAPBGA
標(biāo)準(zhǔn)包裝： 126
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
DSP56303 Technical Data, Rev. 11
1-6
Freescale Semiconductor
Signals/Connections
BG
Input
Ignored Input
Bus Grant—Asserted by an external bus arbitration circuit when the DSP56303
becomes the next bus master. When BG is asserted, the DSP56303 must wait until BB
is deasserted before taking bus mastership. When BG is deasserted, bus mastership is
typically given up at the end of the current bus cycle. This may occur in the middle of an
instruction that requires more than one external bus cycle for execution.
The default operation of this bit requires a setup and hold time as specified in Table 2-
14. An alternate mode can be invoked: set the asynchronous bus arbitration enable
(ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set, BG and BB are
synchronized internally. This eliminates the respective setup and hold time
requirements but adds a required delay between the deassertion of an initial BG input
and the assertion of a subsequent BG input.
BB
Input/
Output
Ignored Input
Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the
pending bus master become the bus master (and then assert the signal again). The
bus master may keep BB asserted after ceasing bus activity regardless of whether BR
is asserted or deasserted. Called “bus parking,” this allows the current bus master to
reuse the bus without rearbitration until another device requires the bus. BB is
deasserted by an “active pull-up” method (that is, BB is driven high and then released
and held high by an external pull-up resistor).
The default operation of this signal requires a setup and hold time as specified in Table
2-14. An alternative mode can be invoked by setting the ABE bit (Bit 13) in the
Operating Mode Register. When this bit is set, BG and BB are synchronized internally.
See BG for additional information.
Note: BB requires an external pull-up resistor.
CAS
Output
Tri-stated
Column Address Strobe—When the DSP is the bus master, CAS is an active-low
output used by DRAM to strobe the column address. Otherwise, if the Bus Mastership
Enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated.
BCLK
Output
Tri-stated
Bus Clock
When the DSP is the bus master, BCLK is active when the Operating Mode Register
Address Trace Enable bit is set. When BCLK is active and synchronized to CLKOUT by
the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle.
BCLK
Output
Tri-stated
Bus Clock Not
When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise,
the signal is tri-stated.
Table 1-8.
External Bus Control Signals (Continued)
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
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