參數(shù)資料
型號(hào)： DSP56303VL100
廠商： Freescale Semiconductor
文件頁數(shù)： 28/108頁
文件大?。?/td> 0K
描述： IC DSP 24BIT 100MHZ 196-MAPBGA
標(biāo)準(zhǔn)包裝： 126
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
DSP56303 Technical Data, Rev. 11
2-6
Freescale Semiconductor
Specifications
2.5.4
Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7.
Reset, Stop, Mode Select, and Interrupt Timing6
No.
Characteristics
Expression
100 MHz
Unit
Min
Max
8
Delay from RESET assertion to all pins at reset value
3
—
26.0
ns
9
Required RESET duration4
Power on, external clock generator, PLL disabled
Power on, external clock generator, PLL enabled
Power on, internal oscillator
During STOP, XTAL disabled (PCTL Bit 16 = 0)
During STOP, XTAL enabled (PCTL Bit 16 = 1)
During normal operation
50
× ETC
1000
× ET
C
75000
× ETC
75000
× ETC
2.5
× T
C
2.5
× TC
500.0
10.0
0.75
25.0
—
ns
s
ms
ns
10
Delay from asynchronous RESET deassertion to first external address
output (internal reset deassertion)5
Minimum
Maximum
3.25
× TC + 2.0
20.25
× TC + 10
34.5
—
212.5
ns
11
Synchronous reset set-up time from RESET deassertion to CLKOUT
Transition 1
Minimum
Maximum
TC
5.9
—
10.0
ns
12
Synchronous reset deasserted, delay time from the CLKOUT Transition
1 to the first external address output
Minimum
Maximum
3.25
× TC + 1.0
20.25
× TC + 1.0
33.5
—
203.5
ns
13
Mode select setup time
30.0
—
ns
14
Mode select hold time
0.0
—
ns
15
Minimum edge-triggered interrupt request assertion width
6.6
—
ns
16
Minimum edge-triggered interrupt request deassertion width
6.6
—
ns
17
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory access address out valid
Caused by first interrupt instruction fetch
Caused by first interrupt instruction execution
4.25
× T
C + 2.0
7.25
× TC + 2.0
44.5
74.5
—
ns
18
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-
purpose transfer output valid caused by first interrupt instruction
execution
10
× TC + 5.0
105.0
—
ns
19
Delay from address output valid caused by first interrupt instruction
execute to interrupt request deassertion for level sensitive fast
interrupts
1, 7, 8
(WS + 3.75)
× T
C – 10.94
—
Note 8
ns
20
Delay from RD assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
(WS + 3.25)
× T
C – 10.94
—
Note 8
ns
21
Delay from WR assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
DRAM for all WS
SRAM WS = 1
SRAM WS = 2, 3
SRAM WS
≥ 4
(WS + 3.5)
× TC – 10.94
(WS + 3.5)
× T
C – 10.94
(WS + 3)
× TC – 10.94
(WS + 2.5)
× TC – 10.94
—
Note 8
ns
22
Synchronous interrupt set-up time from IRQA, IRQB, IRQC, IRQD, NMI
assertion to the CLKOUT Transition 2
5.9
TC
ns
23
Synchronous interrupt delay time from the CLKOUT Transition 2 to the
first external address output valid caused by the first instruction fetch
after coming out of Wait Processing state
Minimum
Maximum
8.25
× T
C + 1.0
24.75
× TC + 5.0
83.5
—
252.5
ns
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