參數(shù)資料
型號(hào)： DSP56303VL100
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 19/108頁(yè)
文件大?。?/td> 0K
描述： IC DSP 24BIT 100MHZ 196-MAPBGA
標(biāo)準(zhǔn)包裝： 126
系列： DSP563xx
類(lèi)型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤(pán)
DSP56303 Technical Data, Rev. 11
1-14
Freescale Semiconductor
Signals/Connections
1.10 Serial Communication Interface (SCI)
The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals
such as modems.
Table 1-14.
Serial Communication Interface
Signal Name
Type
State During
Reset1,2
Signal Description
RXD
PE0
Input
Input or Output
Ignored Input
Serial Receive Data—Receives byte-oriented serial data and transfers it to the
SCI Receive Shift Register.
Port E 0—The default configuration following reset is GPIO input PE0. When
configured as PE0, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal RXD through the Port E
Control Register.
TXD
PE1
Output
Input or Output
Ignored Input
Serial Transmit Data—Transmits data from the SCI Transmit Data Register.
Port E 1—The default configuration following reset is GPIO input PE1. When
configured as PE1, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal TXD through the Port E
Control Register.
SCLK
PE2
Input/Output
Input or Output
Ignored Input
Serial Clock—Provides the input or output clock used by the transmitter and/or
the receiver.
Port E 2—The default configuration following reset is GPIO input PE2. When
configured as PE2, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal SCLK through the Port
E Control Register.
Notes:
1.
In the Stop state, the signal maintains the last state as follows:
If the last state is input, the signal is an ignored input.
If the last state is output, the signal is tri-stated.
2.
The Wait processing state does not affect the signal state.
3.
All inputs are 5 V tolerant.
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