參數(shù)資料
型號(hào)： DSP56303VL100
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 64/108頁(yè)
文件大?。?/td> 0K
描述： IC DSP 24BIT 100MHZ 196-MAPBGA
標(biāo)準(zhǔn)包裝： 126
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
AC Electrical Characteristics
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
2-39
453
TXC rising edge to transmitter 0 drive enable assertion
—
34.0
20.0
x ck
i ck
ns
454
TXC rising edge to data out valid
—
20.0
8
10.0
x ck
i ck
ns
455
TXC rising edge to data out high impedance
3
—
31.0
16.0
x ck
i ck
ns
456
TXC rising edge to Transmitter 0 drive enable deassertion
3
—
34.0
20.0
x ck
i ck
ns
457
FST input (bl, wr) set-up time before TXC falling edge
2
2.0
21.0
—
x ck
i ck
ns
458
FST input (wl) to data out enable from high impedance
—
27.0
—
ns
459
FST input (wl) to Transmitter 0 drive enable assertion
—
31.0
—
ns
460
FST input (wl) set-up time before TXC falling edge
2.5
21.0
—
x ck
i ck
ns
461
FST input hold time after TXC falling edge
4.0
0.0
—
x ck
i ck
ns
462
Flag output valid after TXC rising edge
—
32.0
18.0
x ck
i ck
ns
Notes:
1.
For the internal clock, the external clock cycle is defined by Icyc (see Timing 7) and the ESSI Control Register.
2.
The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform,
but spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last
bit clock of the first word in the frame.
3.
Periodically sampled and not 100 percent tested
4.
VCC = 3.3 V ± 0.3 V; TJ = 40°C to +100 °C, CL = 50 pF
5.
TXC (SCK Pin) = transmit clock
RXC (SC0 or SCK pin) = receive clock
FST (SC2 pin) = transmit frame sync
FSR (SC1 or SC2 pin) receive frame sync
6.
i ck = internal clock
x ck = external clock
i ck a = internal clock, Asynchronous mode
(asynchronous implies that TXC and RXC are two different clocks)
i ck s = Internal Clock, Synchronous mode
(synchronous implies that TXC and RXC are the same clock)
7.
bl = bit length; wl = word length; wr = word length relative.
8.
If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay is 20 ns + (0.5
× T
C).
9.
An expression is used to compute the number listed as the minimum or maximum value as appropriate.
Table 2-18.
ESSI Timings (Continued)
No.
Characteristics4, 5, 7
Symbol
Expression9
100 MHz
Cond-
ition5
Unit
Min
Max
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