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參數(shù)資料
| 型號(hào)： | DSP56004ROM |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | Symphony音頻DSP系列的24位數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 50/82頁(yè) |
| 文件大?。?/td> | 636K |
| 代理商： | DSP56004ROM |
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2-26
DSP56004/D, Rev. 3
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
163 First SCK Edge to
HREQ In Not Asserted
(HREQ In Hold Time)
master
0
0
—
0
—
0
—
ns
Note:
1.
For an Internal Clock frequency below 33 MHz, the minimum permissible Internal Clock to Serial Clock
frequency ratio is 4:1. For an Internal Clock frequency above 33 MHz, the minimum permissible Internal Clock
to Serial Clock frequency ratio is 6:1.
In CPHA = 1 mode, the SPI slave supports data transfers at t
SPICC
= 3
×
T
C
, if the user assures that the HTX
is written at least T
C
ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave
supports data transfers at t
SPICC
= 3
×
T
C
, if the user assures that the HTX is written at least T
C
ns before
the first edge of SCK of each word.
When CPHA = 1, the SS line may remain active low between successive transfers.
Periodically sampled, not 100% tested
2.
3.
4.
Figure 2-17
SPI Master Timing (CPHA = 0)
Table 2-12
Serial Host Interface (SHI) SPI Protocol Timing (Continued)
No.
Characteristics
Mode
Filter
Mode
Expression
50 MHz
66 MHz
81 MHz
Unit
Min Max Min Max Min
Max
SS
(Input)
SCK (CPOL = 0)
(Output)
SCK (CPOL = 1)
(Output)
MISO
(Input)
Valid
MOSI
(Output)
MSB
Valid
LSB
MSB
LSB
HREQ
(Input)
141
142
143
144
144
141
144
144
143
142
148
149
149
148
152
153
163
161
AA0271
F
Freescale Semiconductor, Inc.
n
.
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