
DS26522 Dual T1/E1/J1 Transceiver
85 of 258
FRAMER REGISTER LIST
ADDRESS
085h
086h
087h
088h
089h
08Ah
08B
08Ch–08Fh
090h
091h
092h
093
094h
095h
NAME
RESCR
ERCNT
RHFC
RIBOC
T1RSCC
RXPC
RBPBS
—
RLS1
RLS2
RLS3
RLS4
RLS5
—
RLS7
RLS7
—
RSS1
RSS2
RSS3
RSS4
T1RSCD1
T1RSCD2
—
RIIR
RIM1
RIM2
RIM3
RIM3
RIM4
RIM5
—
RIM7
—
RSCSE1
RSCSE2
RSCSE3
RSCSE4
T1RUPCD1
T1RUPCD2
T1RDNCD1
T1RDNCD2
RRTS1
—
RRTS3
RRTS3
—
RRTS5
RHPBA
RHF
—
RBCS1
DESCRIPTION
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
—
Receive Elastic Store Control Register
Error-Counter Configuration Register
Receive HDLC FIFO Control Register
Receive Interleave Bus Operation Control Register
In-Band Receive Spare Control Register (T1 Mode Only)
Receive Expansion Port Control Register
Receive BERT Port Bit Suppress Register
Reserved
Receive Latched Status Register 1
Receive Latched Status Register 2
Receive Latched Status Register 3
Receive Latched Status Register 4
Receive Latched Status Register 5 (HDLC)
Reserved
Receive Latched Status Register 7 (T1 Mode)
Receive Latched Status Register 7 (E1 Mode)
Reserved
Receive-Signaling Status Register 1
Receive-Signaling Status Register 2
Receive-Signaling Status Register 3
Receive-Signaling Status Register 4 (E1 Mode Only)
Receive Spare Code Definition Register 1 (T1 Mode Only)
Receive Spare Code Definition Register 2 (T1 Mode Only)
Reserved
Receive Interrupt Information Register
Receive Interrupt Mask Register 1
Receive Interrupt Mask Register 2 (E1 Mode Only)
Receive Interrupt Mask Register 3 (T1 Mode)
Receive Interrupt Mask Register 3 (E1 Mode)
Receive Interrupt Mask Register 4
Receive Interrupt Mask Register 5 (HDLC)
Reserved
Receive Interrupt Mask Register 7 (T1 Mode)
Reserved
Receive-Signaling Change of State Enable Register 1
Receive-Signaling Change of State Enable Register 2
Receive-Signaling Change of State Enable Register 3
Receive-Signaling Change of State Enable Register 4 (E1 Mode Only)
Receive Up Code Definition Register 1 (T1 Mode Only)
Receive Up Code Definition Register 2 (T1 Mode Only)
Receive Down Code Definition Register 1 (T1 Mode Only)
Receive Down Code Definition Register 2 (T1 Mode Only)
Receive Real-Time Status Register 1
Reserved
Receive Real-Time Status Register 3 (T1 Mode)
Receive Real-Time Status Register 3 (E1 Mode)
Reserved
Receive Real-Time Status Register 5 (HDLC)
Receive HDLC Packet Bytes Available Register
Receive HDLC FIFO Register
Reserved
Receive Blank Channel Select Register 1
096h
R/W
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
0A1h
—
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
0A2h
R/W
0A3h
0A4h
0A5h
0A6h
0A7h
0A8h
0A9h
0AAh
0ABh
0ACh
0ADh
0AEh
0AFh
0B0h
0B1h
R/W
R/W
—
R/W
—
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R
—
0B2h
R
0B3h
0B4h
0B5h
0B6h
—
R
R
R
—
R/W
0B7h–0BFh
0C0h