
DS26522 Dual T1/E1/J1 Transceiver
3 of 258
8.9.8
8.9.9
8.9.10
8.9.11
8.9.12
8.9.13
8.9.14
8.9.15
8.9.16
8.9.17
8.10
8.10.1
8.10.2
8.11
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
8.12
8.12.1
8.12.2
9.
9.1
9.1.1
9.1.2
9.1.3
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.3
9.4
9.4.1
9.4.2
9.5
9.6
10.
10.1
10.2
10.3
10.4
11.
11.1
11.2
12.
12.1
12.1.1
12.1.2
12.2
12.3
E1 Automatic Alarm Generation .......................................................................................................... 54
Error-Count Registers.......................................................................................................................... 55
DS0 Monitoring Function...................................................................................................................... 57
Transmit Per-Channel Idle Code Insertion........................................................................................... 58
Receive Per-Channel Idle Code Insertion............................................................................................ 58
Per-Channel Loopback ........................................................................................................................ 58
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)................................................................... 58
T1 Programmable In-Band Loop Code Generator............................................................................... 59
T1 Programmable In-Band Loop Code Detection................................................................................ 60
Framer Payload Loopbacks................................................................................................................. 61
HDLC C
ONTROLLERS
................................................................................................................62
Receive HDLC Controller..................................................................................................................... 62
Transmit HDLC Controller.................................................................................................................... 65
L
INE
I
NTERFACE
U
NITS
(LIU
S
)....................................................................................................67
LIU Operation....................................................................................................................................... 69
Transmitter........................................................................................................................................... 70
Receiver............................................................................................................................................... 73
Jitter Attenuator.................................................................................................................................... 76
LIU Loopbacks..................................................................................................................................... 77
B
IT
-E
RROR
-R
ATE
T
EST
(BERT) F
UNCTION
................................................................................79
BERT Repetitive Pattern Set ............................................................................................................... 80
BERT Error Counter............................................................................................................................. 80
DEVICE REGISTERS .....................................................................................................81
R
EGISTER
L
ISTINGS
......................................................................................................................81
Global Register List.............................................................................................................................. 82
Framer Register List............................................................................................................................. 83
LIU and BERT Register List................................................................................................................. 90
R
EGISTER
B
IT
M
APS
......................................................................................................................91
Global Register Bit Map....................................................................................................................... 91
Framer Register Bit Map...................................................................................................................... 92
LIU Register Bit Map.......................................................................................................................... 100
BERT Register Bit Map...................................................................................................................... 100
G
LOBAL
R
EGISTER
D
EFINITIONS
..................................................................................................101
F
RAMER
R
EGISTER
D
EFINITIONS
.................................................................................................109
Receive Register Definitions.............................................................................................................. 109
Transmit Register Definitions............................................................................................................. 168
LIU R
EGISTER
D
EFINITIONS
.........................................................................................................203
BERT R
EGISTER
D
EFINITIONS
.....................................................................................................212
FUNCTIONAL TIMING .................................................................................................220
T1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................220
T1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................225
E1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................230
E1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................232
OPERATING PARAMETERS.......................................................................................235
T
HERMAL
C
HARACTERISTICS
....................................................................................................236
L
INE
I
NTERFACE
C
HARACTERISTICS
..........................................................................................236
AC TIMING CHARACTERISTICS ................................................................................237
M
ICROPROCESSOR
B
US
AC C
HARACTERISTICS
........................................................................237
Parallel Port Mode.............................................................................................................................. 237
SPI Bus Mode.................................................................................................................................... 240
JTAG I
NTERFACE
T
IMING
.........................................................................................................248
S
YSTEM
C
LOCK
AC C
HARACTERISTICS
....................................................................................249