
DS26522 Dual T1/E1/J1 Transceiver
136 of 258
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: One-Second Select (1SECS
). This bit allows for synchronization of the error counter updates between
multiple ports. When ERCNT.3 = 0, setting this bit (on a specific framer) will update the framer’s error counters on
the transition of the one-second timer from framer 1. Note that this bit should always be clear for framer 1.
0 = Use the one-second timer that is internal to the framer.
1 = Use the one-second timer from framer 1 to latch updates.
Bit 6: Manual Counter Update Select (MCUS).
When manual update mode is enabled with EAMS, this bit can be
used to allow the incoming LATCH_CNT signal to latch all counters. Useful for synchronously latching counters of
multiple DS26522 cores located on the same die.
0 = MECU is used to manually latch counters.
1 = Counters are latched on the rising edge of the LATCH_CNT signal.
Bit 5: Manual Error Counter Update (MECU).
When enabled by ERCNT.3, the changing of this bit from a 0 to a 1
allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The
user must wait a minimum of 250
μ
s before reading the error count registers to allow for proper update.
Bit 4: Error Counter Update Select (ECUS).
T1 Mode:
0 = Update error counters once a second
1 = Update error counters every 42ms (333 frames)
E1 Mode:
0 = Update error counters once a second
1 = Update error counters every 62.5ms (500 frames)
Bit 3: Error Accumulation Mode Select (EAMS).
0 = Automatic updating of error counters enabled. The state of ERCNT.4 determines accumulation time
(timed update)
1 = User toggling of ERCNT.5 determines accumulation time (manual update)
Bit 2: PCVCR Fs-Bit Error Report Enable (FSBE) (T1 Mode Only).
0 = do not report bit errors in Fs-bit position; only Ft-bit position
1 = report bit errors in Fs-bit position as well as Ft-bit position
Bit 1: Multiframe Out of Sync Count Register Function Select (MOSCRF) (T1 Mode Only).
0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
Bit 0: T1 Line Code Violation Count Register Function Select (LCVCRF).
0 = do not count excessive zeros
1 = count excessive zeros
ERCNT
Error-Counter Configuration Register
086h
7
6
5
4
3
2
1
0
1SECS
1SECS
0
MCUS
MCUS
0
MECU
MECU
0
ECUS
ECUS
0
EAMS
EAMS
0
FSBE
—
0
MOSCRF
—
0
LCVCRF
LCVCRF
0