
DS26522 Dual T1/E1/J1 Transceiver
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: RCLK Invert (RCLKINV).
0 = no inversion
1 = invert RCLK as input
Bit 6: RSYNC Invert (RSYNCINV).
0 = no inversion
1 = invert RSYNC as either input or output
Bit 5: H.100 SYNC Mode (H100EN).
See Section
8.8.3
for more information.
0 = normal operation
1 = RSYNC and TSSYNCIO signals are shifted
Bit 4: RSYSCLK Mode Select (RSCLKM).
0 = if RSYSCLK is 1.544MHz
1 = if RSYSCLK is 2.048MHz or IBO enabled
Bit 3: RSYNC Multiframe Skip Control (RSMS) (T1 Mode Only).
Useful in framing format conversions from D4 to
ESF. This function is not available when the receive-side elastic store is enabled. RSYNC must be set to output
multiframe pulses.
0 = RSYNC will output a pulse at every multiframe
1 = RSYNC will output a pulse at every other multiframe
Bit 2: RSYNC I/O Select (RSIO).
(Note:
This bit must be set to zero when elastic store is disabled) The default
value for this bit is a logic 1 so that the default state of RSYNC is as an input.
0 = RSYNC is an output
1 = RSYNC is an input (only valid if elastic store enabled)
Bit 1: RSYNC Mode Select 2 (RSMS2).
T1 Mode:
RSYNC pin must be programmed in the output frame mode.
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
E1 Mode:
RSYNC pin must be programmed in the output multiframe mode.
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC-4 multiframe boundaries
In E1 mode, RSMS2 also selects which multiframe signal is available at the RMSYNC pin, regardless of the
configuration for RSYNC. When RSMS2 = 0, RMSYNC outputs CAS multiframe boundaries; when RSMS2 = 1,
RMSYNC outputs CRC-4 multiframe boundaries.
Bit 0: RSYNC Mode Select 1 (RSMS1).
Selects frame or multiframe pulse when RSYNC pin is in output mode. In
input mode (elastic store must be enabled) multiframe mode is only useful when receive-signaling reinsertion is
enabled.
0 = frame mode
1 = multiframe mode
RIOCR
Receive I/O Configuration Register
084h
7
6
5
4
3
2
1
0
RCLKINV
RCLKINV
0
RSYNCINV
RSYNCINV
0
H100EN
H100EN
0
RSCLKM
RSCLKM
0
RSMS
—
0
RSIO
RSIO
1
RSMS2
RSMS2
0
RSMS1
RSMS1
0