
DS26522 Dual T1/E1/J1 Transceiver
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NAME
PIN
TYPE
FUNCTION
RCHBLK/
CLK1
J6
RCHBLK/
CLK2
M11
O
Receive Channel Block/Receive Channel Block Clock.
This pin can be
configured to output either RCHBLK or RCHCLK. RCHBLK is a user-
programmable output that can be forced high or low during any of the 24 T1 or 32
E1 channels. It is synchronous with RCLK when the receive-side elastic store is
disabled. It is synchronous with RSYSCLK when the receive-side elastic store is
enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller
in applications where not all channels are used such as fractional service, 384kbps
service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-
and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
RCHCLK.
RCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during
the LSB of each channel. It is synchronous with RCLK when the receive-side
elastic store is disabled. It is synchronous with RSYSCLK when the receive-side
elastic store is enabled. It is useful for parallel-to-serial conversion of channel data.
Backplane Clock.
Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK
from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an
external reference clock. This allows for the IBO clock to reference from external
source or T1J1E1 recovered clock or the MCLK oscillator.
BPCLK1
K6
BPCLK2
M10
O
MICROPROCESSOR INTERFACE
A12
A8
A7
A6
A5
A4
A3
A2
A1
A0
E1
E2
F1
F2
G1
G2
H1
H2
J1
J2
I
Address [12], [8:0].
This bus selects a specific register in the DS26522 during
read/write access. A12 is the MSB and A0 is the LSB.
D[7]/
SPI_CPOL
K1
I
Data [7]/SPI Interface Clock Polarity
D[7]:
Bit 7 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when both
CSB1
and
CSB2
= 1.
SPI_CPOL:
This signal selects the clock polarity when SPI_SEL = 1. See Section
8.1.3
for detailed timing and functionality information. Default setting is low.
D[6]/
SPI_CPHA
K2
I
Data [6]/SPI Interface Clock Phase
D[6]:
Bit 6 of the 16-bit or 8-bit data bus used to input data during register writes,
and data outputs during register reads. Not driven when both
CSB1
and
CSB2
= 1.
SPI_CPHA:
This signal selects the clock phase when SPI_SEL = 1. See Section
8.1.3
for detailed timing and functionality information. Default setting is low.
D[5]/
SPI_SWAP
L1
I
Data [5]/SPI Bit Order Swap
D[5]:
Bit 5 of the 16-bit or 8-bit data bus used to input data during register writes,
and data outputs during register reads. Not driven when both
CSB1
and
CSB2
= 1.
SPI_SWAP:
This signal is active when SPI_SEL = 1. The address and data bit
order is swapped when SPI_SWAP is high. The R/W and B bit positions are never
changed in the control word.
0 = MSB is transmitted and received first.
1 = LSB is transmitted and received first.
Data [4].
Bit 4 of the 8-bit data bus used to input data during register writes, and
data outputs during register reads. Not driven when both
CSB1
and
CSB2
= 1.
Data [3].
Bit 3 of the 8-bit data bus used to input data during register writes, and
data outputs during register reads. Not driven when both
CSB1
and
CSB2
= 1.
D[4]
L2
I
D[3]
M1
I