參數(shù)資料
型號(hào)： DM9000A
廠商： Electronic Theatre Controls, Inc.
英文描述： Ethernet Controller with General Processor Interface
中文描述： 以太網(wǎng)控制器與通用處理器接口
文件頁(yè)數(shù)： 35/56頁(yè)
文件大?。?/td> 1744K
代理商： DM9000A
DM9000A
Ethernet Controller with General Processor Interface
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
35
generator circuit. When waking up from Sleep mode (write
this bit to 0), the configuration will go back to the state
before sleep; but the state machine will be reset
Remote Loopout Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
16.0
RLOUT
0, RW
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
Bit Name
Default
17.15
100FDX
1, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100M full
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not
in the auto-negotiation mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100M half
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not
in the auto-negotiation mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M Full
Duplex mode. The software can read bit [15:12] to see which
mode is selected after auto-negotiation. This bit is invalid when it
is not in the auto-negotiation mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M half
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not
in the auto-negotiation mode
Reserved
Read as 0, ignore on write
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of
the address (bit 4). A station management entity connected to
multiple PHY entities must know the appropriate address of each
PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
17.14
100HDX
1, RO
17.13
10FDX
1, RO
17.12
10HDX
1, RO
17.11-17
.9
17.8-17.
4
Reserved
0, RO
PHYADR
[4:0]
(PHYADR),
RW
17.3-17.
0
ANMB[3:
0]
0, RO
相關(guān)PDF資料
PDF描述
DM9000AE Ethernet Controller with General Processor Interface
DM9000AEP Ethernet Controller with General Processor Interface
DM9000 ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY
DM9000E ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY
DM9006CJ Gate Expander
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9000A_06 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface
DM9000AE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface
DM9000AEP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:網(wǎng)絡(luò)接口電路
DM9000B 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller With General Processor Interface
DM9000B_12 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller With General Processor Interface
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*