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參數資料
| 型號： | DM9000A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ethernet Controller with General Processor Interface |
| 中文描述： | 以太網控制器與通用處理器接口 |
| 文件頁數： | 19/56頁 |
| 文件大小： | 1744K |
| 代理商： | DM9000A |
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DM9000A
Ethernet Controller with General Processor Interface
6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode)
Bit
Name
Type
7:6
RESERVED
0,RO
Reserved
When set, it enables Link Status Change Wake up Event
This bit will not be affected after software reset
When set, it enables Sample Frame Wake up Event
This bit will not be affected after software reset
When set, it enables Magic Packet Wake up Event
This bit will not be affected after software reset
When set, it indicates that Link Change and Link Status Change Event occurred
This bit will not be affected after software reset
When set, it indicates that the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after software reset
When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset
6.16 Physical Address Register ( 10H~15H )
Bit
Name
Default
7:0
PAB5
E,RW
Physical Address Byte 5 (15H)
7:0
PAB4
E,RW
Physical Address Byte 4 (14H)
7:0
PAB3
E,RW
Physical Address Byte 3 (13H)
7:0
PAB2
E,RW
Physical Address Byte 2 (12H)
7:0
PAB1
E,RW
Physical Address Byte 1 (11H)
7:0
PAB0
E,RW
Physical Address Byte 0 (10H)
6.17 Multicast Address Register ( 16H~1DH )
Bit
Name
Default
7:0
MAB7
X,RW
Multicast Address Byte 7 (1DH)
7:0
MAB6
X,RW
Multicast Address Byte 6 (1CH)
7:0
MAB5
X,RW
Multicast Address Byte 5 (1BH)
7:0
MAB4
X,RW
Multicast Address Byte 4 (1AH)
7:0
MAB3
X,RW
Multicast Address Byte 3 (19H)
7:0
MAB2
X,RW
Multicast Address Byte 2 (18H)
7:0
MAB1
X,RW
Multicast Address Byte 1 (17H)
7:0
MAB0
X,RW
Multicast Address Byte 0 (16H)
6.18 General purpose control Register ( 1EH ) (in 8-bit mode)
Bit
Name
Default
7
RESERVED
PH0,RO
Reserved
General Purpose Control 6~4
Define the input/output direction of pins GP6~4 respectively.
These bits are all forced to “1”s, so pins GP6~4 are output only.
General Purpose Control 3~1
Define the input/output direction of pins GP 3~1 respectively.
When a bit is set 1, the direction of correspondent bit of General Purpose Register
is output. Other defaults are input
0
RESERVED
PH1,RO
Reserved
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
19
Description
5
LINKEN
P0,RW
4
SAMPLEEN
P0,RW
3
MAGICEN
P0,RW
2
LINKST
P0,RO
1
SAMPLEST
P0,RO
0
MAGICST
P0,RO
Description
Description
Description
6:4
GPC64
PH,
111,RO
3:1
GPC31
PH,
000,RW
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相關代理商/技術參數 |
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| DM9000A_06 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
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| DM9000B_12 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller With General Processor Interface |
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