參數(shù)資料
型號: DM9000A
廠商: Electronic Theatre Controls, Inc.
英文描述: Ethernet Controller with General Processor Interface
中文描述: 以太網(wǎng)控制器與通用處理器接口
文件頁數(shù): 33/56頁
文件大小: 1744K
代理商: DM9000A
DM9000A
Ethernet Controller with General Processor Interface
10_FDX
0, RO
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the link partner
0 = 10BASE-T full duplex is not supported by the link
partner
10_HDX
0, RO
10BASE-T Support
1 = 10BASE-T half duplex is supported by the link partner
0 = 10BASE-T half duplex is not supported by the link
partner
Selector
<00000>,
RO
Link partner
s binary encoded protocol selector
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
33
5.6
5.5
5.4-5.0
Protocol Selection Bits
8.7 Auto-negotiation Expansion Register (ANER)- 06
Bit
Bit Name
6.15-6.5
Reserved
Default
0, RO
Description
Reserved
Read as 0, ignore on write
0, RO/LH Local Device Parallel Detection Fault
PDF = 1: A fault detected via parallel detection function.
PDF = 0: No fault detected via parallel detection function
0, RO
Link Partner Next Page Able
LP_NP_ABLE = 1: Link partner, next page available
LP_NP_ABLE = 0: Link partner, no next page
0,RO/P
Local Device Next Page Able
NP_ABLE = 1: DM9000A, next page available
NP_ABLE = 0: DM9000A, no next page
DM9000A does not support this function, so this bit is
always 0
0, RO/LH New Page Received
A new link code word page received. This bit will be
automatically cleared when the register (register 6) is read by
management
0, RO
Link Partner Auto-negotiation Able
A
1
in this bit indicates that the link partner supports
Auto-negotiation
6.4
PDF
6.3
LP_NP_ABL
E
6.2
NP_ABLE
6.1
PAGE_RX
6.0
LP_AN_ABL
E
8.8 DAVICOM Specified Configuration Register (DSCR) - 16
Bit
Bit Name
Default
16.15
BP_4B5B
Description
0,RW
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
16.14
BP_SCR
0, RW
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