參數(shù)資料
型號(hào)： DM9000A
廠商： Electronic Theatre Controls, Inc.
英文描述： Ethernet Controller with General Processor Interface
中文描述： 以太網(wǎng)控制器與通用處理器接口
文件頁(yè)數(shù)： 11/56頁(yè)
文件大小： 1744K
代理商： DM9000A
DM9000A
Ethernet Controller with General Processor Interface
General I/O Ports
Registers GPCR and GPR can program these pins
These pins are input ports at default.
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
11
28,29,31
GP3,GP2,GP1
I/O
5.2 EEPROM Interface
Pin No.
Pin Name
Type
I/O,PD IO Data to EEPROM
Clock to EEPROM
This pin is also used as the strap pin of the polarity of the INT pin
When this pin is pulled high, the INT pin is low active; otherwise the INT pin is
high active
Chip Select to EEPROM
This pin is also used as a strap pin to define the internal memory data
bus width. When it is pulled high, the memory access bus is 8-bit;
Otherwise it is 16-bit.
Description
19
EEDIO
20
EECK
O,PD
21
EECS
O,PD
5.3 Clock Interface
Pin No.
43
Pin Name
X2
Type
O
Description
Crystal 25MHz Out
44
X1
I
Crystal 25MHz In
5.4 LED
I
nterface
Pin No.
Pin Name
Type
Description
39
LED1
O
Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY.
This pin also acts as ISA bus IO16 defined in EEPROM setting in 16-bit
mode.
Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
This pin also acts as ISA bus IOWAIT or WAKE defined in EEPROM
setting in 16-bit mode.
38
LED2
O
5.5 10/100 PHY/Fiber
Pin No.
Pin Name
Type
Description
46
SD
I
Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
Bandgap Ground
48
BGGND
P
1
BGRES
I/O
Bandgap Pin
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