參數(shù)資料
型號(hào)： DM9000A
廠商： Electronic Theatre Controls, Inc.
英文描述： Ethernet Controller with General Processor Interface
中文描述： 以太網(wǎng)控制器與通用處理器接口
文件頁(yè)數(shù)： 34/56頁(yè)
文件大?。?/td> 1744K
代理商： DM9000A
DM9000A
Ethernet Controller with General Processor Interface
BP_ALIGN
0, RW
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and
symbol decoding functions) bypassed. Transmit functions
(symbol encoder and scrambler) bypassed
0 = Normal operation
BP_ADPOK
0, RW
BYPASS ADPOK
Force signal detector (SD) active. This register is for debug
only, not release to customer
1=Forced SD is OK,
0=Normal operation
Reserved
0, RW
Reserved
Force to 0 in application.
TX
1, RW
100BASE-TX Mode Control
1 = 100BASE-TX operation
Reserved
0, RO
Reserved
Reserved
0, RW
Reserved
Force to 0 in application.
F_LINK_100
0, RW
Force Good Link in 100Mbps
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
SPLED_CTL
0, RW
Reserved
Force to 0 in application.
COLLED_CT
L
RPDCTR-EN
1, RW
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 = Disable automatic reduced power down
1 = Enable automatic reduced power down
SMRST
0, RW
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be
reset. This bit is self-clear after reset is completed
MFPSC
1, RW
MF Preamble Suppression Control
Frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
SLEEP
0, RW
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep
mode and power down all circuit except oscillator and clock
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
34
16.13
16.12
16.11
16.10
16.9
16.8
16.7
16.6
16.5
0, RW
Reserved
Force to 0 in application.
16.4
16.3
16.2
16.1
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