參數(shù)資料
型號(hào): DA28F160S5-70
廠商: INTEL CORP
元件分類: DRAM
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: 2M X 8 FLASH 5V PROM, 70 ns, PDSO56
封裝: 16 X 23.70 MM, SSOP-56
文件頁(yè)數(shù): 43/50頁(yè)
文件大?。?/td> 1220K
代理商: DA28F160S5-70
E
6.2.4
28F160S5, 28F320S5
43
ADVANCE INFORMATION
AC CHARACTERISTICS - READ-ONLY OPERATIONS
Table 20. AC Read Characteristics
(1,5)
, T
A
=
–40
o
C to +85
o
C
Versions
(4)
5V ± 5% V
CC
-70/-90
(All units in ns unless otherwise noted)
5V ± 10% V
CC
-80/-100
-100/-110
#
Sym
Parameter
Notes
Min
Max
Min
Max
Min
Max
R1
t
AVAV
Read/Write Cycle Time
16 Mbit
1
70
80
100
32 Mbit
1
90
100
110
R2
t
AVQV
Address to Output Delay
16 Mbit
1
70
80
100
32 Mbit
1
90
100
110
R3
t
ELQV
CE
X
# to Output Delay
16 Mbit
2
70
80
100
32 Mbit
2
90
100
110
R4
t
PHQV
RP# High to Output Delay
400
400
400
R5
t
GLQV
OE# to Output Delay
2
30
35
40
R6
t
ELQX
CE
X
# to Output in Low Z
3
0
0
0
R7
t
EHQZ
CE
X
# High to Output in High Z
3
25
30
35
R8
t
GLQX
OE# to Output in Low Z
3
0
0
0
R9
t
GHQZ
OE# High to Output in High Z
3
10
10
15
R10 t
OH
Output Hold from Address, CE
X
#, or
OE# Change, Whichever Occurs First
3
0
0
0
R11 t
ELFL
t
ELFH
CE
X
# Low to BYTE# High or Low
3
5
5
5
R12 t
FLQV
t
FHQV
BYTE# to Output Delay
16 Mbit
3
70
80
100
32 Mbit
3
90
100
110
R13 t
FLQZ
BYTE# to Output in High Z
3
25
30
30
NOTES:
1.
2.
3.
4.
5.
See AC Input/Output Reference Waveform for maximum allowable input slew rate.
OE# may be delayed up to t
ELQV
-t
GLQV
after the falling edge of CE
X
# without impact on t
ELQV
.
Sampled, not 100% tested.
See Ordering Information for device speeds (valid operational combinations).
See Figures 13 through 15 for testing characteristics.
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