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參數(shù)資料
| 型號： | DA28F160S5-70 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 2M X 8 FLASH 5V PROM, 70 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁數(shù)： | 36/50頁 |
| 文件大小： | 1220K |
| 代理商： | DA28F160S5-70 |
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28F160S5, 28F320S5
E
36
ADVANCE INFORMATION
SR.7 =
0
1
Start
Write 60H,
Block/Device Address
Write 01H/F1H,
Block/Device Address
Full Status
Check if Desired
Set Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
1
0
Read Status Register
Data (See Above)
1
0
Read
Status Register
Voltage Range Error
Bus
Operation
Command
Comments
Standby
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set
before full status is checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Bus
Operation
Command
Comments
Write
Write
Set
Block/Master
Lock-Bit Setup
Data = 01H (Block),
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Read
Data = 60H
Addr = Block Address (Block),
Device Address (Master)
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation
or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
Standby
SR.3 =
SR.4 =
Set Lock-Bit Error
Set Lock-Bit Successful
Set
Block or Master
Lock-Bit Confirm
Status Register Data
Standby
Check SR.4
1 = Set Lock-Bit Error
0
1
Device Protect Error
SR.1 =
1
0
SR.4,5 =
Command Sequence
Error
Check SR.4,5
Both 1 = Command Sequence Error
Standby
Check SR.1
1 = Device Protect Detect
RST# = V
(Set Master Lock-Bit Operation)
RST# = V , Master Lock-Bit Is Set
(Set Block Lock-Bit Operation)
Check SR.3
1 = Programming Voltage Error
Detect
Figure 11. Set Block Lock-Bit Flowchart
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