參數(shù)資料
型號(hào)： DA28F160S5-70
廠商： INTEL CORP
元件分類(lèi)： DRAM
英文描述： 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述： 2M X 8 FLASH 5V PROM, 70 ns, PDSO56
封裝： 16 X 23.70 MM, SSOP-56
文件頁(yè)數(shù)： 15/50頁(yè)
文件大小： 1220K
代理商： DA28F160S5-70
E
NOTES:
1. Bus operations are defined in.Table 2.
2. X = Any valid address within the device.
BA = Address within the block being erased or locked.
IA = Identifier Code Address: see Table 12.
QA = Query database Address.
PA = Address of memory location to be programmed.
3. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from Status Register. See Table 15 for a description of the Status Register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code. (See Table 14.)
4. The upper byte of the data bus (DQ
8
–15
) during command writes is a
“Don’t Care” in x16 operation.
5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See
Section 4.3 for read identifier code data.
6. If a block is locked (i.e., the block’s lock-bit is set to 0), WP# must be at V
in order to perform block erase, program and
suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is V
IL
will fail.
7. Either 40H or 10H are recognized by the WSM as the byte/word program setup.
8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available.
9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1
byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the
correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write
cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the
buffer boundary causes unexpected results and should be avoided.
10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued.
Confirm also reactivates suspended operations.
11. A block lock-bit can be set only while WP# is V
IH
.
12. WP# must be at V
IH
to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.
13. Commands other than those shown above are reserved for future use and should not be used.
14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The
Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
28F160S5, 28F320S5
15
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