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參數(shù)資料
| 型號： | DA28F160S5-70 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 2M X 8 FLASH 5V PROM, 70 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁數(shù)： | 42/50頁 |
| 文件大小： | 1220K |
| 代理商： | DA28F160S5-70 |
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28F160S5, 28F320S5
E
42
ADVANCE INFORMATION
Table 19.
DC Characteristics
(Continued)
Notes
Sym
Parameter
Min
Max
Unit
Conditions
V
IL
Input Low Voltage
7
–0.5
0.8
V
V
IH
Input High Voltage
7
2.0
V
CC
+ 0.5
V
V
OL
Output Low Voltage
3,7
0.45
V
V
CC
= V
CC
Min
I
OL
= 5.8 mA
V
OH1
Output High Voltage (TTL)
3,7
2.4
V
V
CC
= V
CC
Min
I
OH
= –2.5 mA
V
OH2
Output High Voltage (CMOS)
3,7
0.85
×
V
CC
V
V
CC
= V
CC
Min
I
OH
= –2.5 mA
V
CC
– 0.4
V
V
CC
= V
CC
Min
I
OH
= –100 μA
V
PPLK
V
PP
Lockout Voltage
4,7
1.5
V
V
PPH
V
PP
Voltage
4
4.5
5.5
V
V
LKO
V
CC
Lockout Voltage
8
2.0
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V
CC
voltage and T
A
= +25
°
C. These currents are
valid for all product versions (packages and speeds).
2. I
CCWS
and I
CCES
are specified with the device de-selected. If read or programmed while in erase suspend mode, the
device’s current is the sum of I
CCWS
or I
CCES
and I
CCR
or I
CCW
.
3. Includes STS in level RY/BY# mode.
4. Block erase, program, and lock-bit configurations are inhibited when V
PP
≤
V
PPLK
, and not guaranteed in the range between
V
PPLK
(max) and V
PPH
(min), and above V
PPH
(max).
5. Automatic Power Savings (APS) reduces typical I
CCR
to 1 mA at 5V V
CC
static operation.
6. CMOS inputs are either V
CC
± 0.2V or GND ± 0.2V. TTL inputs are either V
IL
or V
IH
.
7. Sampled, not 100% tested.
8. With V
CC
≤
V
LKO
flash memory writes are inhibited.
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