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參數(shù)資料
| 型號(hào)： | CYRF6936-40LFXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | WirelessUSB⑩ LP 2.4 GHz Radio SoC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, MO-220, QFN-40 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 466K |
| 代理商： | CYRF6936-40LFXC |
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CYRF6936
Document #: 38-16015 Rev. *G
Page 7 of 40
Interrupts
The device provides an interrupt (IRQ) output, which is config-
urable to indicate the occurrence of various different events.
The IRQ pin may be programmed to be either active HIGH or
active LOW, and be either a CMOS or open drain output. A full
description of all the available interrupts can be found in
“Register Descriptions” on page 12
.
The CYRF6936 IC features three sets of interrupts: transmit,
receive, and system interrupts. These interrupts all share a
single pin (IRQ), but can be independently enabled/disabled.
The contents of the enable registers are preserved when
switching between transmit and receive modes.
If more than one interrupt is enabled at any time, it is
necessary to read the relevant status register to determine
which event caused the IRQ pin to assert. Even when a given
interrupt source is disabled, the status of the condition that
would otherwise cause an interrupt can be determined by
reading the appropriate status register. It is therefore possible
to use the devices without the IRQ pin by polling the status
registers to wait for an event, rather than using the IRQ pin.
Clocks
A 12 MHz crystal (30 ppm or better) is directly connected
between XTAL and GND without the need for external capac-
itors. A digital clock out function is provided, with selectable
output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output
may be used to clock an external microcontroller (MCU) or
ASIC. This output is enabled by default, but may be disabled.
Listed below are the requirements for the crystal to be directly
connected to XTAL pin and GND.
Nominal Frequency: 12 MHz
Operating Mode: Fundamental Mode
Resonance Mode: Parallel Resonant
Frequency Initial Stability: ±30 ppm
Series Resistance: <60 ohms
Load Capacitance: 10 pF
Drive Level: 10 μW–100 μW
Power Management
The operating voltage of the device is 1.8V to 3.6V DC, which
is applied to the V
BAT
pin. The device can be shut down to a
fully static sleep mode by writing to the FRC END = 1 and END
STATE = 000 bits in the XACT_CFG_ADR register over the
SPI interface. The device enters sleep mode within 35 μs after
the last SCK positive edge at the end of this SPI transaction.
Alternatively, the device may be configured to automatically
enter sleep mode after completing packet transmission or
reception. When in sleep mode, the on-chip oscillator is
stopped, but the SPI interface remains functional. The device
wakes from sleep mode automatically when the device is
commanded to enter transmit or receive mode. When
resuming from sleep mode, there is a short delay while the
oscillator restarts. The device can be configured to assert the
IRQ pin when the oscillator has stabilized.
The output voltage (V
REG
) of the Power Management Unit
(PMU) is configurable to several minimum values between
2.4V and 2.7V. V
REG
may be used to provide up to 15 mA
(average load) to external devices. It is possible to disable the
PMU, and to provide an externally regulated DC supply
voltage to the device’s main supply in the range 2.4V to 3.6V.
The PMU also provides a regulated 1.8V supply to the logic.
The PMU is designed to provide high boost efficiency
(74–85% depending on input voltage, output voltage and load)
when using a Schottky diode and power inductor, eliminating
the need for an external boost converter in many systems
where other components require a boosted voltage. However,
reasonable efficiencies (69–82% depending on input voltage,
output voltage, and load) may be achieved when using low
cost components such as SOT23 diodes and 0805 inductors.
The PMU also provides a configurable low battery detection
function, which may be read over the SPI interface. One of
seven thresholds between 1.8V and 2.7V may be selected.
The interrupt pin may be configured to assert when the voltage
on the V
BAT
pin falls below the configured threshold. LV IRQ
is not a latched event. Battery monitoring is disabled when the
device is in sleep mode.
Low Noise Amplifier and Received
Signal Strength Indication
The gain of the receiver can be controlled directly by clearing
the AGC EN bit and writing to the Low Noise Amplifier (LNA)
bit of the RX_CFG_ADR register. Clearing the LNA bit reduces
the receiver gain approximately 20 dB, allowing accurate
reception of very strong received signals (for example when
operating a receiver very close to the transmitter). Approxi-
mately 30 dB of receiver attenuation can be added by setting
the Attenuation (ATT) bit; this allows data reception to be
limited to devices at very short ranges. Disabling AGC and
enabling LNA is recommended unless receiving from a device
using external PA.
When the device is in receive mode the RSSI_ADR register
returns the relative signal strength of the on-channel signal
power.
When receiving, the device automatically measures and
stores the relative strength of the signal being received as a
five bit value. An RSSI reading is taken automatically when the
SOP is detected. In addition, a new RSSI reading is taken
every time the previous reading is read from the RSSI_ADR
register, allowing the background RF energy level on any
given channel to be easily measured when RSSI is read when
no signal is being received. A new reading can occur as fast
as once every 12 μs.
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF6936-40LTXC | 功能描述:USB 接口集成電路 Wireless USB RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CYRF6936-40LTXC | 制造商:Cypress Semiconductor 功能描述:CYRF6936-40LTXC |
| CYRF6936-40LTXCKC | 制造商:Cypress Semiconductor 功能描述: |
| CYRF6936-40LTXCKS | 制造商:Cypress Semiconductor 功能描述: |
| CYRF6936A-40LFXC | 制造商:Cypress Semiconductor 功能描述: |
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