參數(shù)資料
型號(hào)： CYS25G0101DX
廠商： Cypress Semiconductor Corp.
英文描述： SONET OC-48 Transceiver(SONET OC-48收發(fā)器)
中文描述： 與SONET OC - 48收發(fā)器（與SONET OC - 48收發(fā)器）
文件頁(yè)數(shù)： 1/17頁(yè)
文件大小： 279K
代理商： CYS25G0101DX
CYS25G0101DX
SONET OC-48 Transceiver
Cypress Semiconductor Corporation
Document Number: 38-02009 Rev. *K
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 27, 2007
Features
I
SONET OC-48 operation
I
Bellcore and ITU jitter compliance
I
2.488 GBaud serial signaling rate
I
Multiple selectable loopback or loop through modes
I
Single 155.52 MHz reference clock
I
Transmit FIFO for flexible data interface clocking
I
16-bit parallel-to-serial conversion in transmit path
I
Serial-to-16-bit parallel conversion in receive path
I
Synchronous parallel interface
LVPECL compliant
HSTL compliant
I
Internal transmit and receive phase-locked loops (PLLs)
I
Differential CML serial input
50 mV input sensitivity
100
Internal termination and DC restoration
I
Differential CML serial output
Source matched for 50
transmission lines (100
differential
transmission lines)
I
Direct interface to standard fiber optic modules
I
Less than 1.0W typical power
I
120-pin 14 mm × 14 mm TQFP
I
Standby power saving mode for inactive loops
I
0.25
μ
BiCMOS technology
I
Pb-free packages available
Functional Description
The CYS25G0101DX SONET OC-48 Transceiver is a commu-
nications building block for high speed SONET data communica-
tions. It provides complete parallel-to-serial and serial-to-parallel
conversion, clock generation, and clock and data recovery
operations in a single chip optimized for full SONET compliance.
Transmit Path
New data is accepted at the 16-bit parallel transmit interface at
a rate of 155.52 MHz. This data is passed to a small integrated
FIFO to allow flexible transfer of data between the SONET
processor and the transmit serializer. As each 16-bit word is read
from the transmit FIFO, it is serialized and sent out to the high
speed differential line driver at a rate of 2.488 Gbits/second.
Receive Path
As serial data is received at the differential line receiver, it is
passed to a clock and data recovery (CDR) PLL that extracts a
precision low jitter clock from the transitions in the data stream.
This bit rate clock is used to sample the data stream and receive
the data. Every 16-bit times, a new word is presented at the
receive parallel interface along with a clock.
Parallel Interface
The parallel I/O interface supports high speed bus communica-
tions using HSTL signaling levels to minimize both power
consumption and board landscape. The HSTL outputs are
capable of driving unterminated transmission lines of less than
70 mm and terminated 50
transmission lines of more than twice
that length.
The CYS25G0101DX Transceiver’s parallel HSTL I/O can also
be configured to operate at LVPECL signaling levels. This is
done externally by changing V
DDQ
, V
REF
and creating a simple
circuit at the termination of the transceiver’s parallel output
interface.
相關(guān)PDF資料
PDF描述
CYT101 Voltage and Current Controller
CYT2606E20E PFM Step-Up DC-DC Converter
CYT2606E20F PFM Step-Up DC-DC Converter
CYT2606E20T PFM Step-Up DC-DC Converter
CYT2606E21E PFM Step-Up DC-DC Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYS25G0101DX_07 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:SONET OC-48 Transceiver
CYS25G0101DX_10 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:SONET OC-48 Transceiver
CYS25G0101DX-AEXC 功能描述:電信線路管理 IC SONET OC-48 Transceiver RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYS25G0101DX-ATC 制造商:Cypress Semiconductor 功能描述:SONET Transceiver 1TX 1RX 2.488GBd 120-Pin TQFP
CYS25G0101DX-ATI 制造商:Cypress Semiconductor 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*