參數(shù)資料
型號(hào)： CYRF6936-40LFXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： WirelessUSB⑩ LP 2.4 GHz Radio SoC
中文描述： SPECIALTY TELECOM CIRCUIT, QCC40
封裝： 6 X 6 MM, LEAD FREE, MO-220, QFN-40
文件頁(yè)數(shù)： 25/40頁(yè)
文件大?。?/td> 466K
代理商： CYRF6936-40LFXC
CYRF6936
Document #: 38-16015 Rev. *G
Page 25 of 40
Mnemonic
TX_OFFSET_MSB_ADR
Address
1
0x1C
Bit
7
6
5
4
3
2
0
Default
-
-
-
-
0
0
0
0
Read/Write
-
-
-
-
R/W
R/W
R/W
R/W
Function
Not Used
Not Used
Not Used
Not Used
STRIM MSB
Bits 7:4
Bits 3:0
Not Used.
The most significant 4 bits of the synthesizer trim value. Typically, this register is loaded with 0x05 during initialization.
Mnemonic
MODE_OVERRIDE_ADR
Address
1
0x1D
Bit
7
6
5
4
3
2
0
Default
0
0
0
0
0
-
-
0
Read/Write
W
W
W
W
W
-
-
W
Function
RSVD
RSVD
FRC SEN
FRC AWAKE
Not Used
Not Used
RST
Bits 7:6
Bit 5
Reserved. Must be zero.
Manually Initiate Synthesizer. Setting this bit forces the synthesizer to start. Clearing this bit has no effect. For this bit to operate
correctly, the oscillator must be running before this bit is set.
Force Awake. Force the device out of sleep mode. Setting both bits of this field forces the oscillator to keep running at all times
regardless of the END STATE setting. Clearing both of these bits disables this function.
Not Used.
Reset. Setting this bit forces a full reset of the device. Clearing this bit has no effect.
Bits 4:3
Bits 2:1
Bit 0
Mnemonic
RX_OVERRIDE_ADR
Address
1
0x1E
Bit
7
6
5
4
3
2
0
Default
0
0
0
0
0
0
0
-
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
Function
ACK RX
RXTX DLY
MAN RXACK
FRC RXDR
DIS CRC0
DIS RXCRC
ACE
Not Used
This register provides the ability to override some automatic features of the device.
Bit 7
When this bit is set, the device uses the transmit synthesizer frequency rather than the receive synthesizer frequency for the
given channel when automatically entering receive mode.
Bit 6
When this bit is set and ACK EN is enabled, the transmission of the ACK packet is delayed by 20
μ
s.
Bit 5
Force Expected Packet Type. When this bit is set, and the device is in receive mode, the device is configured to receive an
ACK packet at the data rate defined in TX_CFG_ADR.
Bit 4
Force Receive Data Rate. When this bit is set, the receiver ignores the data rate encoded in the SOP symbol, and receives
data at the data rate defined in TX_CFG_ADR.
Bit 3
Reject packets with a zero-seed CRC16. Setting this bit causes the receiver to reject packets with a zero-seed, and accept only
packets with a CRC16 that matches the seed in CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR.
Bit 2
The RX CRC16 checker is disabled. If packets with CRC16 enabled are received, the CRC16 is treated as payload data and
stored in the receive buffer.
Bit 1
Accept Bad CRC16. Setting this bit causes the receiver to accept packets with a CRC16 that do not match the seed in
CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR. An ACK is to be sent regardless of the condition of the received CRC16.
Bit 0
Not Used.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYRF6936-40LTXC 功能描述:USB 接口集成電路 Wireless USB RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CYRF6936-40LTXC 制造商:Cypress Semiconductor 功能描述:CYRF6936-40LTXC
CYRF6936-40LTXCKC 制造商:Cypress Semiconductor 功能描述:
CYRF6936-40LTXCKS 制造商:Cypress Semiconductor 功能描述:
CYRF6936A-40LFXC 制造商:Cypress Semiconductor 功能描述:
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