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參數(shù)資料
| 型號： | CYRF6936-40LFXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | WirelessUSB⑩ LP 2.4 GHz Radio SoC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, MO-220, QFN-40 |
| 文件頁數(shù)： | 28/40頁 |
| 文件大小： | 466K |
| 代理商： | CYRF6936-40LFXC |
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CYRF6936
Document #: 38-16015 Rev. *G
Page 28 of 40
Register Files
Files are written to or read from using nonincrementing burst read or write transactions. In most cases, accessing a file may be
destructive; the file must be completely read/written, otherwise the contents may be altered. When accessing file registers, the
bytes are presented to the bus least significant byte first.
Mnemonic
ANALOG_CTRL_ADR
Address
1
0x39
Bit
7
6
5
4
3
2
0
Default
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Function
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RX INV
ALL SLOW
This register provides the ability to override some automatic features of the device.
Bits 7:2
Reserved. Must be zero.
Bit 1
Receive Invert. When set, the incoming receive data is inverted. Firmware MUST set this bit when interoperability with first gen-
eration devices is desired.
Bit 0
All Slow. When set, the synth settling time for all channels is the same as for slow channels. It is recommended that firmware
set this bit when using GFSK data rate mode.
Mnemonic
TX_BUFFER_ADR
Address
0x20
Length
16 Bytes
R/W
W
Default
0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
The transmit buffer is a FIFO. Writing to this file adds a byte to the packet being sent. Writing more bytes to this file than the packet length in
TX_LENGTH_ADR has no effect, and these bytes are lost. The FIFO accumulates data until it is reset using TX CLR in TX_CTRL_ADR. A
previously sent packet, of 16 bytes or less, can be transmitted if TX_GO is set without resetting the FIFO. The contents of TX_BUFFER_ADR
are not affected by the transmission of an Auto ACK.
Mnemonic
RX_BUFFER_ADR
Address
0x21
Length
16 Bytes
R/W
R
Default
0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
The receive buffer is a FIFO. Received bytes may be read from this file register at any time that it is not empty, but when reading from this file
register before a packet has been completely received care must be taken to ensure that error packets (for example with bad CRC16) are
handled correctly.
When the receive buffer is configured to be overwritten by new packets (the alternative is for new packets to be discarded if the receive buffer
is not empty), similar care must be taken to verify after the packet has been read from the buffer that no part of it was overwritten by a newly
received packet while this file register is being read.
When the VLD EN bit in RX_CFG_ADR is set, the bytes in this file register alternate—the first byte read is data, the second byte is a valid flag
for each bit in the first byte, the third byte is data, the fourth byte valid flags, and so on. In SDR and DDR modes the valid flag for a bit is set if
the correlation coefficient for the bit exceeds the correlator threshold, and is cleared if it does not. In 8DR mode, the MSB of a valid flags byte
indicates whether or not the correlation coefficient of the corresponding received symbol exceeds the threshold. The seven LSBs contain the
number of erroneous chips received for the data.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF6936-40LTXC | 功能描述:USB 接口集成電路 Wireless USB RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CYRF6936-40LTXC | 制造商:Cypress Semiconductor 功能描述:CYRF6936-40LTXC |
| CYRF6936-40LTXCKC | 制造商:Cypress Semiconductor 功能描述: |
| CYRF6936-40LTXCKS | 制造商:Cypress Semiconductor 功能描述: |
| CYRF6936A-40LFXC | 制造商:Cypress Semiconductor 功能描述: |
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