參數(shù)資料
型號(hào): CYRF6936-40LFXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: WirelessUSB⑩ LP 2.4 GHz Radio SoC
中文描述: SPECIALTY TELECOM CIRCUIT, QCC40
封裝: 6 X 6 MM, LEAD FREE, MO-220, QFN-40
文件頁(yè)數(shù): 15/40頁(yè)
文件大?。?/td> 466K
代理商: CYRF6936-40LFXC
CYRF6936
Document #: 38-16015 Rev. *G
Page 15 of 40
Mnemonic
RX_CTRL_ADR
Address
1
0x05
Bit
7
6
5
4
3
2
0
Default
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
RX GO
RSVD
RXB16
IRQEN
RXB8
IRQEN
RXB1
IRQEN
RXBERR
IRQEN
RXC
IRQEN
RXE
IRQEN
Bit 7
Start Receive. Setting this bit causes the device to transition to receive mode. If necessary, the crystal oscillator and synthesizer
start automatically after this bit is set. Firmware must never clear this bit. This bit must not be set again until after it clears. The
recommended method to exit receive mode when an error has occurred is to force END STATE and then dummy read all
RX_COUNT_ADR bytes from RX_BUFFER_ADR or poll RSSI_ADR.SOP (bit 7) until set. See XACT_CFG_ADR and
RX_ABORT_ADR for description.
Reserved. Must be zero.
Buffer Full Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Buffer Half Empty Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Buffer Not Empty Interrupt Enable. RXB1 IRQEN must not be set when RXB8 IRQEN is set and vice versa. See
RX_IRQ_STATUS_ADR for description.
Buffer Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Packet Reception Complete Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Receive Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
[+] Feedback
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