參數(shù)資料
型號(hào)： CYRF6936-40LFXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： WirelessUSB⑩ LP 2.4 GHz Radio SoC
中文描述： SPECIALTY TELECOM CIRCUIT, QCC40
封裝： 6 X 6 MM, LEAD FREE, MO-220, QFN-40
文件頁(yè)數(shù)： 26/40頁(yè)
文件大小： 466K
代理商： CYRF6936-40LFXC
CYRF6936
Document #: 38-16015 Rev. *G
Page 26 of 40
Mnemonic
TX_OVERRIDE_ADR
Address
1
0x1F
Bit
7
6
5
4
3
2
0
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
ACK TX
FRC PRE
RSVD
MAN TXACK
OVRD ACK
DIS TXCRC
RSVD
TX INV
This register provides the ability to override some automatic features of the device.
Bit 7
When this bit is set, the device uses the receive synthesizer frequency rather than the transmit synthesizer frequency for the
given channel when automatically entering transmit mode.
Bit 6
Force Preamble. When this bit is set, the device transmits a continuous repetition of the preamble pattern (see
PREAMBLE_ADR) after TX GO is set. This mode is useful for some regulatory approval procedures. Firmware should set bit
RST of MODE_OVERRIDE_ADR to exit this mode.
Bit 5
Reserved. Must be zero.
Bit 4
Transmit ACK Packet. When this bit is set, the device sends an ACK packet when TX GO is set.
Bit 3
ACK Override. Use TX_CFG_ADR to determine the data rate and the CRC16 used when transmitting an ACK packet.
Bit 2
Disable Transmit CRC16. When set, no CRC16 field is present at the end of transmitted packets.
Bit 1
Reserved. Must be zero.
Bit 0
TX Data Invert. When this bit is set the transmit bitstream is inverted.
Mnemonic
XTAL_CFG_ADR
Address
1
0x26
Bit
7
6
5
4
3
2
0
Default
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Function
RSVD
RSVD
RSVD
RSVD
START DLY
RSVD
RSVD
RSVD
This register provides the ability to override some automatic features of the device.
Bits 7:4
Reserved. Must be zero.
Bit 3
Crystal Startup Delay. Setting this bit, sets the crystal startup delay to 150
μ
s to handle warm restarts of the crystal. Firmware
MUST set this bit during initialization.
Bits 2:0
Reserved. Must be zero.
Mnemonic
CLK_OVERRIDE_ADR
Address
1
0x27
Bit
7
6
5
4
3
2
0
Default
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Function
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXF
RSVD
This register provides the ability to override some automatic features of the device.
Bits 7:2
Reserved. Must be zero.
Bit 1
Force Receive Clock. Streaming applications MUST set this bit during receive mode, otherwise this bit is cleared.
Bit 0
Reserved. Must be zero.
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYRF6936-40LTXC 功能描述:USB 接口集成電路 Wireless USB RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CYRF6936-40LTXC 制造商:Cypress Semiconductor 功能描述:CYRF6936-40LTXC
CYRF6936-40LTXCKC 制造商:Cypress Semiconductor 功能描述:
CYRF6936-40LTXCKS 制造商:Cypress Semiconductor 功能描述:
CYRF6936A-40LFXC 制造商:Cypress Semiconductor 功能描述:
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