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參數(shù)資料
| 型號： | CYRF6936-40LFXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | WirelessUSB⑩ LP 2.4 GHz Radio SoC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, MO-220, QFN-40 |
| 文件頁數(shù)： | 21/40頁 |
| 文件大小： | 466K |
| 代理商： | CYRF6936-40LFXC |
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CYRF6936
Document #: 38-16015 Rev. *G
Page 21 of 40
Mnemonic
XACT_CFG_ADR
Address
0x0F
Bit
7
6
5
4
3
2
1
0
Default
1
-
0
0
0
0
0
0
Read/Write
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
Function
ACK EN
Not Used
FRC END
END STATE
ACK TO
Bit 7
Acknowledge Enable. When this bit is set, an ACK packet is automatically transmitted whenever a valid packet is received; in
this case the device is considered to be in transaction mode. After transmission of the ACK packet, the device automatically
transitions to the END STATE. When this bit is cleared, the device transitions directly to the END STATE immediately after the
end of packet transmission. This bit affects both transmitting and receiving devices.
Force End State. Setting this bit forces a transition to the state set in END STATE. By setting the desired END STATE at the
same time as setting this bit the device may be forced to immediately transition from its current state to any other state. This bit
is automatically cleared upon completion. Firmware MUST never try to force END STATE while TX GO is set, nor when RX GO
is set and a SOP has already been received (packet reception already in progress).
Transaction End State. This field defines the mode to which the device transitions after receiving or transmitting a packet. 000
= Sleep Mode; 001 = Idle Mode; 010 = Synth Mode (TX); 011 = Synth Mode (RX); 100 = RX Mode. In normal use, this field is
typically set to ‘000’ or ‘001’ when the device is transmitting packets, and ‘100’ when the device is receiving packets. Note that
when the device transitions to receive mode as an END STATE, the receiver must still be armed by setting RX GO before the
device can begin receiving data. If the system only supports packets less than or equal to 16 bytes then firmware should exam-
ine RXC IRQ and RXE IRQ to determine the status of the packet. If the system supports packets more than 16 bytes, make
sure that END STATE is not sleep, force RXF = 1, perform receive operation, force RXF = 0, and if necessary set END STATE
back to sleep.
ACK Timeout. When the device is configured for transaction mode, this field sets the timeout period after transmission of a
packet during which an ACK must be correctly received in order to prevent a transmit error condition from being detected. This
timeout period is expressed in terms of a number of SOP_CODE_ADR code lengths; if SOP LEN is set, then the timeout period
is this value multiplied by 64
μ
s and if SOP LEN is cleared then the timeout is this value multiplied by 32
μ
s. 00 = 4x; 01 = 8x,
10 = 12x; 11 = 15x the SOP_CODE_ADR code length. ACK_TO must be set to greater than 30 + Data Code Length (only for
8DR) + Preamble Length + SOP Code Length (x2).
Bit 5
Bits 4:2
Bits 1:0
Mnemonic
FRAMING_CFG_ADR
Address
0x10
Bit
7
6
5
4
3
2
1
0
Default
1
0
1
0
0
1
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SOP EN
SOP LEN
LEN EN
SOP TH
Bit 7
SOP Enable. When this bit is set, each transmitted packet begins with a SOP field, and only packets beginning with a valid
SOP field are received. If this bit is cleared, no SOP field is generated when a packet is transmitted, and packet reception
begins whenever two successive correlations against the DATA_CODE_ADR code are detected.
SOP PN Code Length. When this bit is set the SOP_CODE_ADR code length is 64 chips. When this bit is cleared the
SOP_CODE_ADR code length is 32 chips.
Packet Length Enable. When this bit is set the 8 bit value contained in TX_LENGTH_ADR is transmitted immediately after the
SOP field. In receive mode, the 8 bits immediately following the SOP field are interpreted as the length of the packet. When this
bit is cleared no packet length field is transmitted. 8DR always sends the packet length field (LEN EN setting is ignored). GFSK
requires user set LEN EN = 1.
SOP Correlator Threshold. This is the receive data correlator threshold used when attempting to detect a SOP symbol. There
is a single threshold for the SOP_CODE_ADR code. This threshold is applied independently to each of SOP1 and SOP2 fields.
When SOP LEN is set, all 5 bits of this field are used. When SOP LEN is cleared, the most significant bit is disregarded. Typical
applications configure SOP TH = 04h for SOP32 and SOP TH = 0Eh for SOP64.
Bit 6
Bit 5
Bits 4:0
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF6936-40LTXC | 功能描述:USB 接口集成電路 Wireless USB RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CYRF6936-40LTXC | 制造商:Cypress Semiconductor 功能描述:CYRF6936-40LTXC |
| CYRF6936-40LTXCKC | 制造商:Cypress Semiconductor 功能描述: |
| CYRF6936-40LTXCKS | 制造商:Cypress Semiconductor 功能描述: |
| CYRF6936A-40LFXC | 制造商:Cypress Semiconductor 功能描述: |
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