參數(shù)資料
型號(hào): CYP15G0401DXA
廠商: Cypress Semiconductor Corp.
英文描述: Quad HOTLink II Transceiver
中文描述: 四HOTLink II收發(fā)器
文件頁數(shù): 35/48頁
文件大?。?/td> 1115K
代理商: CYP15G0401DXA
CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 35 of 48
CYP15G0401DXA REFCLK Switching Characteristics
Over the Operating Range
Parameter
Description
Min.
Max.
Unit
f
REF
t
REFCLK
t
REFH
REFCLK Clock Frequency
10
150
MHz
REFCLK Period
6.6
100
ns
REFCLK HIGH Time (TXRATE = HIGH)
5.9
70
ns
REFCLK HIGH Time (TXRATE = LOW)
2.9
35
ns
t
REFL
REFCLK LOW Time (TXRATE = HIGH)
5.9
70
ns
REFCLK LOW Time (TXRATE = LOW)
2.9
35
ns
t
REFD[21]
t
REFR [17, 18, 19]
t
REFF [17, 18, 19]
t
TREFDS
t
TREFDH
t
RREFDA
t
RREFDH
t
REFADS
t
REFADH
t
REFCDS
t
REFCDH
t
REFRX
REFCLK Duty Cycle
30
70
%
REFCLK Rise Time (20%-80%)
0.3
5
ns
REFCLK Fall Time (20%-80%)
0.3
5
ns
Transmit Data or TXRST Setup Time to
REFCLK (TXCKSEL
=
LOW)
Transmit Data or TXRST Hold Time from REFCLK
(TXCKSEL
=
LOW)
Receive Data Access Time from REFCLK (RXCKSEL
=
LOW)
Receive Data Hold Time from REFCLK
(RXCKSEL
=
LOW)
1.5
ns
1
ns
9.5
ns
4.0
ns
Received Data Setup Time to RXCLKA (RXCKSEL = LOW)
2
ns
Received Data Hold Time from RXCLKA (RXCKSEL = LOW)
1.5
ns
Received Data Setup Time to RXCLKC (RXCKSEL = LOW)
3
ns
Received Data Hold Time from RXCLKC (RXCKSEL = LOW)
REFCLK Frequency Referenced to Received Clock Period
[22]
0.5
ns
0.02
+0.02
%
CYP15G0401DXA Transmit Serial Outputs and TX PLL Characteristics
Over the Operating Range
Parameter
Description
Condition
Min.
Max.
Unit
t
B
t
RISE
Bit Time
CML Output Rise Time 20
80% (CML Test Load)
[17]
5000
660
ps
SPDSEL = HIGH
50
250
ps
SPDSEL = MID
100
500
ps
SPDSEL = LOW
200
1000
ps
t
FALL
CML Output Fall Time 80
20% (CML Test Load)
[17]
SPDSEL = HIGH
50
250
ps
SPDSEL = MID
100
500
ps
SPDSEL = LOW
200
1000
ps
t
DJ
t
RJ
t
TXLOCK
Deterministic Jitter (peak-peak)
[17, 23]
Random Jitter (
σ
)
[17, 24]
35
ps
8
ps
Transmit PLL lock to REFCLK
TBD
TBD
ns
Notes:
21. The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLK duty
cycle cannot be as large as 30%-70%,
22. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
REFCLK must be within
±
200 PPM (
±
0.02%) of the transmitter PLL reference (REFCLK) frequency, necessitating a
±
100-PPM crystal.
23. While sending continuous K28.5s, outputs loaded to a balanced 100
load, over the operating range.
24. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the
operating range.
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