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參數(shù)資料
| 型號： | CYP15G0401DXA |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quad HOTLink II Transceiver |
| 中文描述： | 四HOTLink II收發(fā)器 |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 1115K |
| 代理商： | CYP15G0401DXA |
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CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 15 of 48
CYP15G0401DXA HOTLink-II Operation
The CYP15G0401DXA is a highly configurable device de-
signed to support reliable transfer of large quantities of data,
using high-speed serial links, from one or multiple sources to
one or multiple destinations. This device supports four single-
byte or single-character channels that may be combined to
support transfer of wider buses.
CYP15G0401DXA Transmit Data Path
Operating Modes
The transmit path of the CYP15G0401DXA supports four
character-wide data paths. These data paths are used in mul-
tiple operating modes as controlled by the TXMODE[1:0] in-
puts.
Input Register
Within these operating modes, the bits in the Input Register for
each channel support different bit assignments, based on if the
character is unencoded, encoded with two control bits, or en-
coded with three control bits. These assignments are shown
in
Table 1
.
Each input register captures a minimum of eight data bits and
two control bits on each input clock cycle. When the encoder
is bypassed, the control bits are part of the pre-encoded 10-bit
character.
When the Encoder is enabled (TXMODE[1]
≠
L), the
TXCTx[1:0] bits are interpreted along with the associated
TXDx[7:0] character to generate the specific 10-bit transmis-
sion character. When TXMODE[0]
≠
H, an additional special
character select (SCSEL) input is also captured and interpret-
ed. This SCSEL input is used to modify the encoding of the
associated characters. When the transmit input registers are
clocked by a common clock (TXCLKA
↑
or REFCLK
↑
), this
SCSEL input can be changed on a clock-by-clock basis and
effects all four channels.
When operated with a separate input clock on each transmit
channel, this SCSEL input is sampled synchronous to
TXCLKA
↑
. While the value on SCSEL still effects all channels,
it is interpreted when the character containing it is read from
the transmit Phase-Align Buffer (where all four paths are inter-
nally clocked synchronously).
Phase-Align Buffer
Data from the input registers is passed either to the encoder
or to the associated Phase-Align buffer. When the transmit
paths are operated synchronous to REFCLK
↑
(TXCKSEL = L
and TXRATE = LOW), the Phase-Align Buffers are bypassed
and data is passed directly to the parity check and encoder
blocks to reduce latency.
When an Input-Register clock with an uncontrolled phase re-
lationship to REFCLK is selected (TXCKSEL
≠
L) or if data is
captured on both edges of REFCLK (TXRATE = HIGH), the
Phase-Align Buffers are enabled. These buffers are used to
absorb clock phase differences between the presently select-
ed input clock and the internal character clock.
Initialization of these phase-align buffers takes place when the
TXRST input is sampled LOW by TXCLKA
↑
. When TXRST is
returned HIGH, the present input clock phase relative to
REFCLK
↑
is set. TXRST is an asynchronous input, but is sam-
pled internally to synchronize it to the internal transmit path
state machines. TXRST must be sampled LOW by a minimum
of two consecutive TXCLKA
↑
clocks to ensure the reset oper-
ation is initiated correctly on all channels.
Once set, the input clocks are allowed to skew in time up to
half a character period in either direction relative to REFCLK
↑
;
i.e.,
±
180
°
. This time shift allows the delay paths of the char-
acter clocks (relative to REFLCK
↑
) to change due to operating
voltage and temperature, while not affecting the design oper-
ation.
If the phase offset, between the initialized location of the input
clock and REFCLK
↑
, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on the associ-
ated TXPERx output. This output will indicate a continuous
error until the Phase-Align Buffer is reset. While the error re-
mains active, the transmitter for the associated channel will
output a continuous C0.7 character to indicate to the remote
receiver that an error condition is present in the link.
In specific transmit modes it is also possible to reset the
Phase-Align Buffers individually and with minimal disruption of
the serial data stream. When the transmit interface is config-
ured for generation of atomic Word Sync Sequences
(TXMODE[1] = M) and a Phase-Align Buffer error is present,
the transmission of a Word Sync Sequence will re-center the
buffer and clear the error condition.
NOTE
: One or more K28.5 characters may be added or lost
from the data stream during this reset operation. When
used with non-Cypress devices that require a complete 16-
character Word Sync Sequence for proper receive Elastic-
ity Buffer alignment, it is recommend that the sequence be
followed by a second Word Sync Sequence to ensure prop-
er operation.
Parity Support
In addition to the ten data and control bits that are captured at
each channel, a TXOPx input is also available on each chan-
nel. This allows the CYP15G0401DXA to support ODD parity
Table 1. Input Register Bit Assignments
[3]
Signal Name
TXDx[0]
(LSB)
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
(MSB)
SCSEL
Unencoded
DINx[0]
DINx[1]
DINx[2]
DINx[3]
DINx[4]
DINx[5]
DINx[6]
DINx[7]
DINx[8]
DINx[9]
N/A
Encoded
2-bit
Control
TXDx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
N/A
3-bit
Control
TXDx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
SCSEL
Note:
3.
The TXOPx inputs are also captured in the associated input register, but their interpretation is under the separate control of PARCTL.
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| CYP15G0401DXA-BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II Transceiver |
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