參數(shù)資料
型號: CYP15G0401DXA
廠商: Cypress Semiconductor Corp.
英文描述: Quad HOTLink II Transceiver
中文描述: 四HOTLink II收發(fā)器
文件頁數(shù): 33/48頁
文件大?。?/td> 1115K
代理商: CYP15G0401DXA
CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 33 of 48
Note:
11.
12. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
13. The common mode range defines the allowable range of REFCLK+ and REFCLK
(relative to the associated power rail) when
|(REFCLK+)
(REFCLK
)| = 0V. This marks the zero-crossing between the true and complement inputs as the signal switches between HIGH and LOW.
14. Maximum I
is measured with V
= MAX, RFEN = LOW, with all serial channels sending a constant alternating 01 pattern, and outputs unloaded. Typical
I
CC
is measured under similar conditions except with V
CC
= 3.3V, T
A
= 25
°
C.
CYP15G0401DXA DC Electrical Characteristics
Over the Operating Range
(continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
AC Test Loads and Waveforms
Notes:
15. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
16. The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the respective rising or falling signal edge crosses this
threshold voltage.
2.0V
0.8V
3.0V
V
th
=1.4V
GND
2.0V
0.8V
(a) LVTTL AC Test Load
(b) CML AC Test Load
< 1 ns
< 1 ns
80%
20%
80%
20%
(c) LVTTL Input Test Waveform
(d) PECL Input Test Waveform
C
L
R
L
R
L
=100
C
< 5 pF
(Includes fixture and
probe capacitance)
V
IHE
3.0V
V
IHE
V
ILE
V
ILE
[15]
[15]
250 ps
250 ps
Note 16
V
th
=1.4V
3.3V
OUTPUT
R1
R2
C
L
R1=365
R2=267
C
L
7 pF
(Includes fixture and
probe capacitance)
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