參數(shù)資料
型號(hào)： CYP15G0401DXA
廠商： Cypress Semiconductor Corp.
英文描述： Quad HOTLink II Transceiver
中文描述： 四HOTLink II收發(fā)器
文件頁(yè)數(shù)： 20/48頁(yè)
文件大?。?/td> 1115K
代理商： CYP15G0401DXA
CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 20 of 48
When configured for local loopback (LPEN = HIGH), the output
drivers for all enabled ports are configured to drive a static
differential logic-1.
Each output can be enabled or disabled separately through the
BOE[7:0] inputs, as controlled by the OELE latch-enable sig-
nal. When OELE is HIGH, the signals present on the BOE[7:0]
inputs are passed through the Serial Output Enable latch to
control the serial output drivers. The BOE[7:0] input associat-
ed with a specific OUTxy
±
driver is listed in
Table 10
.
When OELE is HIGH and BOE[x] is HIGH, the associated se-
rial driver is enabled to drive any attached transmission line.
When OELE is HIGH and BOE[x] is LOW, the associated driv-
er is disabled and internally configured for minimum power dis-
sipation. If both outputs for a channel are in this disabled state,
the associated internal logic for that channel is also configured
for lowest power operation. When OELE returns LOW, the val-
ues present on the BOE[7:0] inputs are latched in the Output
Enable Latch, and remain there until OELE returns HIGH to
opened the latch again.
Note:
When a disabled transmit channel (i.e., both outputs
disabled) is re-enabled, the data on the serial outputs may
not meet all timing specifications for up to 10 ms.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLK input, and
multiples that clock by 10 or 20 (as selected by TXRATE) to
generate a bit-rate clock for use by the transmit shifter. It also
provides a character-rate clock used by the transmit paths.
The clock multiplier PLL can accept a REFCLK input between
10 MHz and 150 MHz, however, this clock range is limited by
the operating mode of the CYP15G0401DXA clock multiplier
(controlled by TXRATE) and by the level on the SPDSEL input.
SPDSEL is a 3-level select
[2]
(ternary) input that selects one
of three operating ranges for the serial data outputs and in-
puts. The operating serial signaling-rate and allowable range
of REFCLK frequencies are listed in
Table 11
.
The REFCLK
±
input is a non-standard input. It is implemented
as a differential input with each input internally biased to
V
CC
/2. If the REFCLK+ input is connected to a TTL, LVTTL, or
LVCMOS clock source, the input signal is recognized when it
passes through the internally biased reference point.
When both the REFCLK+ and REFCLK
inputs are connect-
ed, the clock source must be a differential clock. This can be
Table 9. TX Modes 5 and 8, Quad-Channel Bonded
S
T
T
T
T
T
T
T
T
Characters Generated
X
X
X
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0
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1
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1
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0
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1
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0
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Encoded data character on channel A
K28.5 fill character on channel A
Special character code on channel A
16-character word sync on channel A
Encoded data character on channel B
K28.5 fill character on channel B
Special character code on channel B
16-character word sync on channel B
Encoded data character on channel C
K28.5 fill character on channel C
Special character code on channel C
16-character word sync on channel C
Encoded data character on channel D
K28.5 fill character on channel D
Special character code on channel D
16-character word sync on channel D
16-character word sync on channels A, B, C, and D
Table 10. Output Enable, BIST, and Receive Channel
Enable Signal Map
BOE
Input
BOE[7]
BOE[6]
BOE[5]
BOE[4]
BOE[3]
BOE[2]
BOE[1]
BOE[0]
Output
Controlled
(OELE)
OUTD2
±
OUTD1
±
OUTC2
±
OUTC1
±
OUTB2
±
OUTB1
±
OUTA2
±
OUTA1
±
BIST
Channel
Enable
(BISTLE)
Transmit D
Receive D
Transmit C
Receive C
Transmit B
Receive B
Transmit A
Receive A
Receive PLL
Channel
Enable
(RXLE)
X
Receive D
X
Receive C
X
Receive B
X
Receive A
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參數(shù)描述
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CYP15G0401DXB_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver
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