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參數(shù)資料
| 型號(hào)： | CYP15G0401DXA |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quad HOTLink II Transceiver |
| 中文描述： | 四HOTLink II收發(fā)器 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 1115K |
| 代理商： | CYP15G0401DXA |
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CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 24 of 48
The LFSR is initialized by the BIST hardware once the BIST
enable for that receive channel is present at the output of the
BIST Enable Latch, and is recognized. This sets the BIST
LFSR to the BIST-loop start-code of D0.0 (D0.0 is sent only
once per BIST loop). The status of the BIST progress and any
character mismatches is presented on the RXSTx[2:0] status
outputs.
Code rule violations or running disparity errors that occur as
part of the BIST loop do not cause an error indication.
RXSTx[2:0] indicates 010b or 100b for one character period per
BIST loop to indicate loop completion. This status can be used to
check test pattern progress. These same status values are present-
ed when the decoder is bypassed and BIST is enabled on a receive
channel.
The specific status reported by the BIST state machine are
listed in
Table 21
. These same codes are reported on the re-
ceive status outputs regardless of the state of DECMODE.
The specific patterns checked by each receiver are described
in detail in the Cypress application note
“
HOTLink Built-In Self-
Test.
”
The sequence compared by the CYP15G0401DXA is
identical to that in the CY7B933 and CY7C924DX, allowing
interoperable systems to be built when used at compatible se-
rial signaling rates.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state ma-
chine aborts the compare operations and resets the LFSR to
the D0.0 state to look for the start of the BIST sequence again.
When the receive paths are configured for common clock op-
eration (RXCKSEL
≠
MID) each pass must be preceded by a
16-character Word Sync Sequence to allow output buffer
alignment and management of clock frequency variations.
This is automatically generated by the transmitter when its lo-
cal RXCKSEL
≠
MID.
The BIST state machine requires the characters to be correctly
framed for it to detect the BIST sequence. If the framer is en-
abled and configured for low-latency operation (RFMODE =
LOW), the framer can align to characters within the BIST se-
quence. If either of the multi-byte framers are enabled
(RFMODE
≠
LOW), it is generally necessary to frame the re-
ceiver before BIST is enabled. If the receive outputs are
clocked relative to REFCLK (RXCKSEL = LOW), the transmit-
ter precedes every 511 character BIST sequence with a 16-
character Word Sync Sequence. This sequence will frame the
receiver regardless of the setting of RFMODE.
Receive Elasticity Buffer
Each receive channel contains an Elasticity Buffer that is de-
signed to support multiple clocking modes. These buffers allow
data to be read using an Elasticity Buffer read-clock that is
asynchronous in both frequency and phase from the Elasticity
Buffer write clock, or to use a read clock that is frequency co-
herent but with uncontrolled phase relative to the Elasticity
Buffer write clock.
Each Elasticity Buffer is a minimum of 10-characters deep, and
supports a 12-bit wide data path. It is capable of supporting a
decoded character, three status bits, and a parity bit for each
character present in the buffer. The write clock for these buffers
is always the recovered clock for the associated read channel.
The read clock for the Elasticity Buffers may come from one of
three selectable sources. It may be a
character-rate REFCLK
↑
recovered clock from the same receive channel
recovered clock from an alternate receive channel
These Elasticity Buffers are also used to align the output data
streams when multiple channels are bonded together.
Receive Modes
The operating mode of the receive path is set through the
RXMODE[1:0] inputs. These RXMODE[1:0] inputs are only in-
terpreted when the decoder is enabled (DECMODE
≠
LOW).
These modes determine the type (if any) of channel bonding
and status reporting. The different receive modes are listed in
Table 15
.
Independent Channel Modes
In independent channel modes (RX Modes 0 and 2, where
RXMODE[1] = LOW), all four receive paths may be clocked in
any clock mode selected by RXCKSEL.
When RXCKSEL = LOW, all four receive channels are clocked
by REFCLK. RXCLKB
±
and RXCLKD
±
outputs are disabled
(High-Z), and the RXCLKA
±
and RXCLKC
±
outputs present a
buffered and delayed form of REFCLK. In this mode, the re-
ceive Elasticity Buffers are enabled. For REFCLK
↑
clocking,
the Elasticity Buffers must be able to insert K28.5 characters
and delete framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time on any channel, however, the actual timing
on these insertions and deletions is controlled in part by the
how the transmitter sends its data. Insertion of a K28.5 char-
acter can only occur when the receiver has a framing character
in the Elasticity Buffer. Likewise, to delete a framing character,
one must also be in the Elasticity Buffer. To prevent a receive
buffer overflow or underflow on a receive channel, a minimum
density of framing characters must be present in the received
data streams.
Prior to reception of valid data, at least one Word Sync Se-
quence (or that portion of one necessary to align the receive
buffers) must be received to allow the receive Elasticity Buffer
to be centered. The Elasticity buffer may also be set by a de-
vice reset operation initiated through the TRSTZ input, howev-
er, following such an event the CYP15G0401DX will normally
Table 15. Receive Operating Modes
RX Mode
Operating Mode
M
N
R
[
Channel
Bonding
Independent
RXSTx Status Reporting
Status A
Reserved for test
Status B
Status A
Reserved for test
Status B
Status A
Reserved for test
Status B
0
1
2
3
4
5
6
7
8
LL
LM
LH
ML
MM
MH
HL
HM
HH
Independent
Dual
Dual
Quad
Quad
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0401DXB | PREMIUM VGA CABLE W/AUDIO3FT, HD15 & 3.5MM M-M |
| CYP15G0401DXB-BGC | PREMIUM VGA CABLE W/AUDIO5FT, HD15 & 3.5MM M-M |
| CYP15G0401DXB-BGI | Quad HOTLink II Transceiver |
| CYP15G0401DXA-BGC | Quad HOTLink II Transceiver |
| CYP15G0401DXA-BGI | Quad HOTLink II Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0401DXA-BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II Transceiver |
| CYP15G0401DXA-BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II Transceiver |
| CYP15G0401DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II Transceiver |
| CYP15G0401DXB_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver |
| CYP15G0401DXB-BGC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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