參數(shù)資料
型號(hào): CYP15G0401DXA
廠商: Cypress Semiconductor Corp.
英文描述: Quad HOTLink II Transceiver
中文描述: 四HOTLink II收發(fā)器
文件頁(yè)數(shù): 14/48頁(yè)
文件大?。?/td> 1115K
代理商: CYP15G0401DXA
CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 14 of 48
TRSTZ
LVTTL Input,
internal pull-up
Test Port and Device Reset. Active LOW. Initializes the JTAG controller and all state
machines and counters in the device.
When asserted (LOW), this input asynchronously resets the JTAG test access port
controller.
When sampled LOW by the rising edge of REFLCK, this input resets the internal state
machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is
removed (TRSTZ sampled HIGH by REFCLK
), the status and data outputs will be-
come deterministic in less than 16 REFCLK cycles.
The BISTLE, OELE, and RXLE latches will be reset by TRSTZ.
Power
V
CC
GND
+3.3V Power
Signal and Power Ground for all internal circuits.
Pin Descriptions
CYP15G0401DXA Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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