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參數(shù)資料
| 型號： | CYNSE70256 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁數(shù)： | 97/126頁 |
| 文件大?。?/td> | 3302K |
| 代理商： | CYNSE70256 |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 97 of 126
14.2
Figure 14-2
shows how to cascade up to four blocks. Each block except the last contains up to eight CYNSE70032 devices. The
interconnection within each has been shown in the previous subsection with the cascading of up to eight devices in a block.
Note
.
The interconnection between blocks for depth-cascading is important. For each Search, a block asserts BHO[2], BHO[1], and
BHO[0]. The BHO[2:0] signals for a block are taken only from the last device in the block. For all other devices within that block,
these signals stay open and floating. The host ASIC must program the TLSZ field to 10 in each of the devices for cascading up
to 31 devices (in up to four blocks).
Depth-Cascading up to 31 Devices (Four Blocks)
14.3
Bit[0] of each of the 68-bit entries is designated as a special bit (1 = occupied; 0 = empty). For each Learn or PIO Write to the
data array, each device asserts FULO[1] and FULO[0] if it does not have any empty locations within it (see
Figure 14-3
). Each
device combines the FULO signals from the devices above it with its own full status to generate a FULL signal, which will then
give a full status of the table up to the device asserting the FULL signal.
Figure 14-3
shows the hardware connection diagram for
generating the FULL signal that goes back to the ASIC. In a depth-cascaded block of up to eight devices, the FULL signal from
the last device should be fed back to the ASIC controller to indicate the fullness of the table. The FULL signal of the other devices
should be left open.
Note
. The Learn instruction is supported for up to eight devices, whereas FULL cascading is allowed for one
block in tables containing more than eight devices. In tables for which a Learn instruction will not be used, the bit[0] of each 68-bit
entry should always be set to 1.
Depth-Cascading for a FULL Signal
BHO[2]
Block of 8 CYNSE70032s Block 0 (devices 0–7)
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
BHI[2]
Block of 7 CYNSE70032s Block 3 (devices 24-30)
BHO[2]
BHO[1]
BHI[1]
BHI[0]
GND
BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70032s Block 1 (devices 8–15)
BHO[2]
Block of 8 CYNSE70032s Block 2 (devices 16–23)
BHO[2]
BHO[1]
DQ[67:0]
CMD[8:0], CMDV
SRAM
BHO[1]
BHO[0]
BHO[0]
SSF, SSV
Figure 14-2. Depth-Cascading Four Blocks
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