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參數(shù)資料
| 型號(hào)： | CYNSE70256 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁(yè)數(shù)： | 20/126頁(yè) |
| 文件大?。?/td> | 3302K |
| 代理商： | CYNSE70256 |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 20 of 126
The single Read operation takes six clock cycles that are performed in the following sequence.
Cycle 1
: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the DQ bus supplies
the address as shown in
Table 12-4
and
Table 12-5
. The host ASIC selects the CYNSE70032 device for which ID[4:0] matches
the DQ[25:21] lines. If DQ[25:21] = 11111, the host ASIC selects the CYNSE70032 with the LDEV bit set. The host ASIC also
supplies SADR[21:19] on CMD[8:6] in cycle A of the Read instruction if the Read is directed to the external SRAM.
Cycle 2
: The host ASIC floats DQ[67:0] to a three-state condition.
Cycle 3
: The host ASIC keeps DQ[67:0] in a three-state condition.
Cycle 4
: The selected device starts to drive the DQ[67:0] bus, and drives the ACK signal from Z to low.
Cycle 5
: The selected device drives the Read data from the addressed location on the DQ[67:0] bus, and drives the ACK
signal high.
Cycle 6
: The selected device floats the DQ[67:0] to a three-state condition and drives the ACK signal low.
At the termination of cycle 6, the selected device releases the ACK line to a three-state condition. The Read instruction is
complete, and a new operation can begin.
Note
. The latency of the SRAM Read will be different than the one described above
(see Subsection 15.2, “SRAM PIO Access” on page 99).
Table 12-4
lists and describes the format of the Read address for a data
array, mask array, or SRAM.
Table 12-5
describes the Read address format for the internal registers.
Figure 12-2
illustrates the timing diagram for the burst
Read of the data or mask array.
Table 12-4. Read Address Format for Data Array, Mask Array, or SRAM
DQ
[67:30]
Reserved 0: Direct
DQ
[29]
DQ
[28:26]
SSR Index
(applicable if
DQ[29] is
indirect)
SSR Index
(applicable if
DQ[29] is
indirect)
SSR Index
(applicable if
DQ[29] is
indirect)
DQ
[25:21]
ID
DQ
[20:19]
00: Data
Array
DQ
[18:14]
Reserved If DQ[29] is 0, this field carries the address of the data array
location. If DQ[29] is 1, the SSR Index specified on
DQ[28:26] is used to generate the address of the data array
location: {SSR[13:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
[6]
Reserved If DQ[29] is 0, this field carries the address of the mask array
location. If DQ[29] is 1, the SSR Index specified on
DQ[28:26] is used to generate the address of the mask array
location: {SSR[13:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
[6]
Reserved If DQ[29] is 0, this field carries the address of the SRAM
location. If DQ[29] is 1, the SSR Index specified on
DQ[28:26] is used to generate the address of the SRAM
location: {SSR[13:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
[6]
DQ[13:0]
1: Indirect
Reserved 0: Direct
1: Indirect
ID
01: Mask
Array
Reserved 0: Direct
1: Indirect
ID
10:
External
SRAM
Note:
6.
“ | ” stands for logical OR operation. “{}” stands for concatenation operator.
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
Read
Address
X
Data
CLK2X
CMDV
CMD[1:0]
ACK
DQ
CMD[8:2]
A
B
PHS_L
Figure 12-1. Single-Location Read Cycle Timing
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PDF描述 |
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| CZET101 | Clock Driver |
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| CZEZ101 | Triple Peripheral Driver |
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| CZT122 | TRANSISTOR | BJT | DARLINGTON | NPN | 100V V(BR)CEO | 5A I(C) | SOT-223 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYNSE70256-66BGC | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70256-66BHC | 制造商:Cypress Semiconductor 功能描述:COMMUNICATIONS, NETWORK SEARCH ENGINE - Trays |
| CYONS10017-LBXC | 制造商:Cypress Semiconductor 功能描述: |
| CYONS1001G-LBXC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CYONS1001L | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:OvationONS⑩ 1L - Laser Navigation Sensor |
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