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參數(shù)資料
| 型號(hào)： | CYNSE70256 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁(yè)數(shù)： | 95/126頁(yè) |
| 文件大?。?/td> | 3302K |
| 代理商： | CYNSE70256 |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 95 of 126
The Learn operation lasts two CLK cycles. The sequence of operation is as follows.
Cycle 1A
: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1. The CMD[5:2] field specifies the index
of the comparand register pair that will be written to the data array in the 136-bit-configured table. For a Learn in a 68-bit-con-
figured table, the even-numbered comparand specified by this index will be written. CMD[8:6] carries the bits that will be driven
on SADR[21:19] in the SRAM Write cycle.
Cycle 1B
: The host ASIC continues to drive CMDV to 1, CMD[1:0] to 11, and CMD[5:2] with the comparand pair index. CMD[6]
must be set to 0 if the Learn is being performed on a 68-bit-configured table, and to 1 if the Learn is being performed on a
136-bit-configured table.
Cycle 2
: The host ASIC drives CMDV to 0.
Table 13-25. SRAM Write Cycle Latency from Second Cycle of Learn Instruction
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Latency in CLK Cycles
4
5
6
cycle
1
Learn1
Learn2
CLK2X
CMDV
CMD[1:0]
DQ
SADR[21:0]
CE_L
CMD[8:2]
X
WE_L
OE_L
X
X
X
X
X
TLSZ = 01, LRAM = 1, LDEV = 1.
Figure 13-71. Learn Timing Diagram on Device Number 7 (TLSZ = 01)
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
X
X
1A1B
Comp1
Comp2
X
PHS_L
1
1
0
z
z
z
z
z
z
z
z
z
0
0
SSV
SSF
1
1
1
0
z
1
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYNSE70256-66BGC | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70256-66BHC | 制造商:Cypress Semiconductor 功能描述:COMMUNICATIONS, NETWORK SEARCH ENGINE - Trays |
| CYONS10017-LBXC | 制造商:Cypress Semiconductor 功能描述: |
| CYONS1001G-LBXC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CYONS1001L | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:OvationONS⑩ 1L - Laser Navigation Sensor |
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