參數(shù)資料
型號(hào)： CY7C9689-AC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： TAXI Compatible HOTLink Transceiver
中文描述： 1 CHANNEL(S), 200M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 9/48頁(yè)
文件大?。?/td> 1009K
代理商： CY7C9689-AC
CY7C9689
9
10
RXFULL
Three-state TTL out-
put, changes following
RXCLK
|
Receive FIFO Full Flag.
When the Receive FIFO is enabled (FIFOBYP is HIGH) and its flags are driven
(CE is LOW), RXFULL is asserted when space is available for four or fewer
characters to be written to the HOTLink Receive FIFO. If the RXCLK input is not
continuous or the FIFO is accessed at a rate slower than data is being received,
RXFULL may also indicate that some data has been lost because of FIFO
overflow.
When the Receive FIFO is bypassed (FIFOBYP is LOW), RXFULL is deassert-
ed to indicate that valid data may be present. RXFULL is also used as a BIST
progress indicator, and pulses once every pass through the 511 character BIST
loop.
When RXBISTEN is asserted (LOW), RXFULL becomes the receive BIST loop
progress indicator (regardless of the logic state of FIFOBYP). While RXBISTEN
is asserted, RXFULL is asserted until the receiver detects the start of the BIST
pattern. Then RXFULL is deasserted for the duration of the BIST pattern, puls-
ing asserted for one RXCLK period on the last symbol of each BIST loop. If 14
of 28 consecutive symbols are received in error, RXFULL returns to the asserted
state until the start of a BIST pattern is again detected.
The asserted state of this output (HIGH or LOW) is determined by the state of
the EXTFIFO input. When EXTFIFO is LOW, RXFULL is active LOW. When
EXTFIFO is HIGH, RXFULL is active HIGH.
Receive FIFO Half-full Flag.
When the Receive FIFO is enabled (FIFOBYP is HIGH and CE is LOW)
RXHALF is asserted when the HOTLink Receive FIFO is
half full (128 char-
acters is half full). If a Receive FIFO reset has been initiated (RXRST was
sampled asserted for a minimum of seven RXCLK cycles), RXHALF is deas-
serted to enforce the empty/unavailable status of the Receive FIFO during reset.
If FIFOBYP is LOW, RXHALF remains deasserted having no logical function.
RXHALF is forced to the High-Z state only during a
“
full-chip
”
reset (i.e., while
RESET is LOW).
Receive FIFO Empty Flag.
When the Receive FIFO is enabled (FIFOBYP is HIGH) and its flags are driven
(CE is LOW), RXEMPTY is asserted when the HOTLink Receive FIFO has no
data to forward to the parallel interface. If a Receive FIFO reset has been initi-
ated (RXRST was sampled asserted for a minimum of seven RXCLK cycles),
RXEMPTY is asserted to enforce the empty/unavailable status of the Receive
FIFO during reset.
Any read operation occurring when RXEMPTY is asserted results in no change
in the FIFO status, and the data from the last valid read remains on the RXDATA
bus. When the Receive FIFO is bypassed but the decoder is enabled,
RXEMPTY is used as a valid data indicator. When deasserted it indicates that
valid data is present at the RXDATA or RXCMD outputs as indicated by RXSC/D.
When asserted it indicates that a SYNC character (JK or LM) is present on the
RXCMD output pins. When the Receive FIFO is bypassed (FIFOBYP is LOW),
RXEMPTY is deasserted whenever data is ready.
The asserted state of this output (HIGH or LOW) is determined by the state of
the EXTFIFO input. When EXTFIFO is LOW, RXEMPTY is active LOW. When
EXTFIFO is HIGH, RXEMPTY is active HIGH.
19
RXHALF
Three-state TTL out-
put, changes following
RXCLK
|
21
RXEMPTY
Three-state TTL out-
put, changes following
RXCLK
|
Pin Descriptions
(continued)
Pin
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料
PDF描述
CY7C9689-AI TAXI Compatible HOTLink Transceiver
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CY8C21223 PSoC Mixed-Signal Array(PSoC混合信號(hào)陣列)
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