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參數(shù)資料
| 型號： | CY7C9689-AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | TAXI Compatible HOTLink Transceiver |
| 中文描述： | 1 CHANNEL(S), 200M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大小： | 1009K |
| 代理商： | CY7C9689-AC |
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CY7C9689
12
Analog I/O and Control
89, 90,
81, 82
OUTB±
OUTA±
PECL compatible
differential output
Differential Serial Data Outputs.
These PECL-compatible differential outputs are capable of driving terminated
transmission lines or commercial fiber-optic transmitter modules. To minimize
the power dissipation of unused outputs, the outputs should be left unconnected
and the associated CURSETA or CURSETB should be connected to V
DD
.
Differential Serial Data Inputs.
These inputs accept the serial data stream for deserialization and decoding.
Only one serial stream at a time may be fed to the receive PLL to extract the
data content. This stream is selected using the A/B input.
Current-set Resistor Input for OUTA±.
A precision resistor is connected between this input and a clean ground to set
the output differential amplitude and currents for the OUTA± differential driver.
Current-set Resistor Input for OUTB±.
A precision resistor is connected between this input and a clean ground to set
the output differential amplitude and currents for the OUTB± differential driver.
Carrier Detect Input.
Used to allow an external device to signify a valid signal is being presented to
the high-speed PECL input buffers, as is typical on an Optical Module. When
CARDET is deasserted LOW, the LFI
indicator asserts LOW signifying a Link
Fault. This input can be tied HIGH for copper media applications.
Input A or Input B Selector.
When HIGH, input INA± is selected, when LOW,
INB± is selected.
Link Fault Indication Output. Active LOW.
LFI changes synchronous with RXCLK. This output is driven LOW when the
serial link currently selected by A/B is not suitable for data recovery. This could
be because:
1. Serial Data Amplitude is below acceptable levels
2. Input transition density is not sufficient for PLL clock recovery
3. Input Data stream is outside an acceptable frequency range of operation
4. CARDET is LOW
Diagnostic Loop Back Selector.
When DLB is LOW, LOOP Mode is OFF. Output of the transmitter shifter is
routed to both OUTA± and OUTB± and the serial input selected by A/B is routed
to the receive PLL for data recovery.
When DLB is HIGH, Diagnostic Loopback is Enabled. Output of the transmitter
serial data is routed to the receive PLL for data recovery. Primarily used for
System Diagnostic test. The serial inputs are ignored and OUTA± and OUTB±
are both active.
Test Mode Select.
Used to force the part into a diagnostic test mode used for factory ATE test. This
input must be tied HIGH during normal operation.
94, 93,
86, 85
INA±
INB±
PECL compatible
differential input
97
CURSETA
Analog
78
CURSETB
Analog
100
CARDET
PECL input,
asynchronous
2
A/B
Asynchronous
TTL input
3
LFI
Three-state TTL out-
put, changes following
RXCLK
|
5
DLB
Asynchronous
TTL input
1
TEST
Asynchronous
TTL input normally
wired HIGH
Power
80, 87,
88, 95,
96, 98
76, 79,
83, 84,
91, 92,
99
V
DDA
Power for PECL-compatible I/O signals and internal circuits.
V
SSA
Ground for PECL-compatible I/O signals and internal circuits.
Pin Descriptions
(continued)
Pin
Name
I/O Characteristics
Signal Description
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