參數(shù)資料
型號(hào)： CY7C9689-AC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： TAXI Compatible HOTLink Transceiver
中文描述： 1 CHANNEL(S), 200M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 42/48頁(yè)
文件大?。?/td> 1009K
代理商： CY7C9689-AC
CY7C9689
42
abled. When an Rx_Match (or Rx_RstMatch) condition is not
present, these same drivers are disabled (High-Z).
The selection state of the Receive FIFO is entered when an
Rx_Match condition is present, and RXEN transitions from
HIGH to LOW. Once selected, the Receive FIFO remains se-
lected until RXEN is sampled HIGH by the rising edge of
RXCLK input. The selected state initiates a read cycle from the
Receive FIFO and enables the Receive FIFO data onto the
RXDATA bus. This receive interface selection process is
shown in
Figure 10
.
Synchronous With UTOPIA Timing and Control
(Receive FIFO Bypassed)
When the Receive FIFO is bypassed (FIFOBYP is LOW), the
CY7C9689 must still be selected to enable the output drivers
for the RXDATA bus. With the Receive FIFO bypassed, RXCLK
becomes a synchronous output clock operating at the charac-
ter rate.
When CE is sampled LOW and RXRST is sampled HIGH by
the rising edge of RXCLK output, an Rx_Match condition is
generated. This Rx_Match condition continues until CE is
sampled HIGH or RXRST is sampled LOW at the rising edge
of RXCLK.
When an Rx_Match (or Rx_RstMatch) condition is present,
the RXEMPTY and RXFULL output drivers are enabled. With
the Receive FIFO bypassed, these flags normally indicate a
non-empty condition but may indicate empty if a JK or LM
SYNC character is present in the output register and the re-
ceiver discard policy is non-0. When an Rx_Match (or
Rx_RstMatch) condition is not present, these same drivers are
disabled (High-Z).
The selection state of the Receive Output Register is entered
when an Rx_Match condition is present, and RXEN transitions
from HIGH to LOW. Once selected, the Receive Output Reg-
ister remains selected until RXEN is sampled HIGH by the
rising edge of RXCLK output. In the selected state, the output
drivers for the RXDATA outputs are enabled, and new data is
presented to the RXDATA bus on every clock cycle.
Continuous Selection
Continuous Selection is a specialized form of selection which
does not require sequenced assertion of CE and TXEN or
RXEN to select the device for data transfers. In this Continuous
Selection mode, the CE and associated TXEN or RXEN en-
able signal must be asserted when the device is powered up
or during assertion of RESET. So long as these signals remain
asserted, the device remains selected and data is accepted
and presented on every clock cycle.
NOTE:
The use of continuous selection makes it impossible to
reset the respective internal FIFOs, or to access the Serial
Address Register.
FIFO Reset Address Match
When CE and TXRST are both LOW, and this condition is
sampled by the rising edge of TXCLK, a Tx_RstMatch condi-
tion is generated. This Tx_RstMatch condition continues until
CE or TXRST is sampled HIGH by the rising edge of TXCLK.
When a Tx_RstMatch (or Tx_Match) condition is present, the
TXEMPTY and TXFULL output drivers are enabled (just as in
a normal Tx_Match condition). When a Tx_RstMatch (or
Tx_Match) condition is not present, these same drivers are
disabled (High-Z). The Transmit FIFO reset Address Match is
shown in
Figure 11
. Note that although TXRST remains LOW
for more than one clock cycle, the Tx_RstMatch does not be-
cause the CE signal is no longer asserted (LOW).
When CE and RXRST are both LOW, and this condition is
sampled by the rising edge of RXCLK, an Rx_RstMatch con-
dition is generated. This Rx_RstMatch condition continues un-
til CE or RXRST is sampled HIGH, at the rising edge of RX-
D1
D2
D3
RXCLK
CE
Rx_Match
RXEN
Rx_Selected
RXDATA/RXCMD
RXEMPTY
Figure 10. Receive Selection with Receive FIFO Enabled
RXRST
Not Empty
Note 47
Not Empty
[46]
[46]
Note 47
相關(guān)PDF資料
PDF描述
CY7C9689-AI TAXI Compatible HOTLink Transceiver
CY8C21323 PSoC Mixed-Signal Array(PSoC混合信號(hào)陣列)
CY8C21123 PSoC Mixed-Signal Array(PSoC混合信號(hào)陣列)
CY8C21223 PSoC Mixed-Signal Array(PSoC混合信號(hào)陣列)
CY8C21634-24AX PSoC Mixed-Signal Array
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C9915JXC-5 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C9915JXI-1 功能描述:IC CLK BUFF SKEW 8OUT 32PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:RoboClock™ 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類(lèi)型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱(chēng):23S08-5HPGG
CY7C9915JXI-1T 功能描述:IC CLK BUFF SKEW 8OUT 32PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:RoboClock™ 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類(lèi)型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱(chēng):23S08-5HPGG
CY7C9915JXI-5 制造商:Cypress Semiconductor 功能描述:
CY7CD68321C-56LFXC 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*