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參數(shù)資料
| 型號： | CY7C9689-AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | TAXI Compatible HOTLink Transceiver |
| 中文描述： | 1 CHANNEL(S), 200M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大小： | 1009K |
| 代理商： | CY7C9689-AC |
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CY7C9689
14
MHz. When configured for synchronous operation (Receive
FIFO is bypassed) data is clocked out of the Receive Output
register at up to 20 MHz when configured for 8-bit characters,
or 16.67 MHz when configured for 10-bit characters. The re-
ceive interface is also configurable for FIFO flags with either
HIGH or LOW status indication
Oscillator Speed Selection
The CY7C9689 is designed to operate over a two-octave
range of serial signaling rates, covering the 50- to 200-MBaud
range. To cover this wide range, the PLLs are configured into
various sub-regions using the SPDSEL and RANGESEL in-
puts, and to a limited extent the BYTE8/10 input. These inputs
are used to configure the various prescalers and clock dividers
used with the transmit and receive PLLs.
CY7C9689 TAXI HOTLink Transceiver
Block Diagram Description
Transmit Input/Output Register
The CY7C9689 provides a synchronous interface for data and
command inputs, instead of the TAXI
’
s asynchronous strobed
interface. The Transmit Input Register, shown in
Figure 2
, cap-
tures the data and command to be processed by the HOTLink
Transmitter, and allows the input timing to be made compatible
with asynchronous or synchronous host system buses. These
buses can take the form of external FIFOs, state machines, or
other control structures. Data and command present on the
TXDATA[9:0] and TXSC/D inputs are captured at the rising
edge of the selected sample clock. The transmit data bus bit-
assignments vary depending on the data encoding and bus-
width selected. These bus bit-assignments are shown in
Table
1
, and list the functional names of these different signals. Note
that the function of several of these signals changes in different
operating modes. The logical sense of the enable and FIFO
flag signals depends on the intended interface convention and
is set by the EXTFIFO pin.
The transmit interface supports both synchronous and asyn-
chronous clocking modes, each supporting both UTOPIA and
Cascade timing models. The selection of the specific clocking
mode is determined by the RANGESEL and SPDSEL inputs
and the FIFO Bypass (FIFOBYP) signal.
Transmit Input Register
TXEN
TXDATA[7:0]
TXCMD[3:0]
12
TXCLK
REFCLK
Transmit FIFO
Figure 2. Transmit Input Register
14
To Encoder
Block
CE
TXSC/D
Table 1. Transmit Input Bus Signal Map
TXDATA Bus Input Bit
Transmit Encoder Mode
[1]
Encoded 8-bit
Character Stream
[2]
Pre-encoded 10-bit
Character Stream
Encoded 10-bit
Character Stream
[3]
Pre-encoded 12-bit
Character Stream
TXSC/D
TXSC/D
TXSC/D
TXDATA[0]
TXDATA[0]
TXD[0]
[4]
TXDATA[0]
TXD[0]
[5]
TXDATA[1]
TXDATA[1]
TXD[1]
TXDATA[1]
TXD[1]
TXDATA[2]
TXDATA[2]
TXD[2]
TXDATA[2]
TXD[2]
TXDATA[3]
TXDATA[3]
TXD[3]
TXDATA[3]
TXD[3]
TXDATA[4]
TXDATA[4]
TXD[4]
TXDATA[4]
TXD[4]
TXDATA[5]
TXDATA[5]
TXD[5]
TXDATA[5]
TXD[5]
TXDATA[6]
TXDATA[6]
TXD[6]
TXDATA[6]
TXD[6]
TXDATA[7]
TXDATA[7]
TXD[7]
TXDATA[7]
TXD[7]
TXDATA[8]/TXCMD[3]
TXCMD[3]
TXD[8]
TXDATA[8]
TXDATA[9]
[3]
TXD[8]
TXDATA[9]/TXCMD[2]
TXCMD[2]
TXD[9]
TXD[9]
TXD[10]
[5]
TXCMD[1]
TXCMD[1]
TXCMD[1]
TXCMD[0]
TXCMD[0]
TXCMD[0]
TXD[11]
Notes:
1.
2.
All open cells are ignored.
When ENCBYP is HIGH and BYTE8/10 is HIGH, transmitted bit order is the encoded form (MSB to LSB) of TXDATA[7,6,5,4] and TXDATA[3,2,1,0] or
TXCMD[3,2,1,0] as selected by TXSC/D.
When ENCBYP is HIGH and BYTE8/10 is LOW, transmitted bit order is the encoded form (MSB to LSB) of TXDATA[8,7,6,5,4] and TXDATA[9,3,2,1,0] or
TXCMD[1,0] as selected by TXSC/D.
When ENCBYP is LOW and BYTE8/10 is HIGH, the transmitted bit order is (LSB to MSB) TXD[0,1,2,3,4,5,6,7,8,9].
When ENCBYP is LOW and BYTE8/10 is LOW, the transmitted bit order is (LSB to MSB) TXD[0,1,2,3,4,5,6,7,8,9,11,10].
3.
4.
5.
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