參數(shù)資料
型號(hào)： CY7C9689-AC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： TAXI Compatible HOTLink Transceiver
中文描述： 1 CHANNEL(S), 200M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 13/48頁(yè)
文件大小： 1009K
代理商： CY7C9689-AC
CY7C9689
13
CY7C9689 HOTLink Operation
Overview
The CY7C9689 is designed to move parallel data across both
short and long distances with minimal overhead or host sys-
tem intervention. This is accomplished by converting the par-
allel characters into a serial bit-stream, transmitting these se-
rial bits at high speed, and converting the received serial bits
back into the original parallel data format.
The CY7C9689 offers a large feature set, allowing it to be used
in a wide range of host systems. Some of the of configuration
options are
AMD TAXIchip 4B/5B & 5B/6B compatible encoder/decoder
AMD TAXIchip compatible serial link
AMD TAXIchip parallel COMMAND and DATA I/O bus
architecture
8-bit or 10-bit character size
User-definable data packet or frame structure
Two-octave data rate range
Asynchronous (FIFOed) or synchronous data interface
Embedded or bypassable FIFO data storage
Encoded or non-encoded
Multi-PHY capability
This flexibility allows the CY7C9689 to meet the data transport
needs of almost any system.
Transmit Data Path
Transmit Data Interface/Transmit Data FIFO
The transmit data interface to the host system is configurable
as either an asynchronous buffered (FIFOed) parallel interface
or as a synchronous pipeline register. The bus itself can be
configured for operation with either 8-bit or 10-bit character
widths.
When configured for asynchronous operation (where the host-
bus interface clock operates asynchronous to the serial char-
acter and bit stream clocks), the host interface becomes that
of a synchronous FIFO clocked by TXCLK. In this configura-
tion an internal 256-character Transmit FIFO is enabled that
allows the host interface to be written at any rate from DC to
50 MHz.
When configured for synchronous operation, the transmit in-
terface is clocked by REFCLK and operates synchronous to
the internal character and bit-stream clocks. The input register
can be written at either 1/10th or 1/12th the serial bit rate. This
interface can be clocked at up to 40 MHz when configured for
8-bit data width, and up to 33 MHz when configured for 10-bit
data bus width. Actual clock rate depends on data rate as well
as RANGESEL and SPDSEL logic levels.
Both asynchronous and synchronous interface operations
support user control over the logical sense of the FIFO status
flags. Full and empty flags on both the transmitter and receiver
can be active HIGH or active LOW. This facilitates interfacing
with existing control logic or external FIFOs with minimal or no
external glue logic.
Encoder
Data from the host interface or Transmit FIFO is next passed
to an Encoder block. The CY7C9689 contains both 4B/5B and
5B/6B encoders that are used to improve the serial transport
characteristics of the data. For those systems that contain their
own encoder or scrambler, this Encoder may be bypassed.
Serializer/Line Driver
The data from the Encoder is passed to a Serializer. This Se-
rializer operates at 10 or 12 times the character rate. With the
internal FIFOs enabled, REFCLK can run at 1x, 2x, or 4x the
character rate. With the FIFOs bypassed, REFCLK can oper-
ate at 1x or 2x the character rate. The serialized data is output
in NRZI format from two PECL-compatible differential line driv-
ers configured to drive transmission lines or optical modules.
Receive Data Interface
Line Receiver/Deserializer/Framer
Serial data is received at one of two PECL-compatible differ-
ential line receivers. The data is passed to both a Clock and
Data Recovery Phase Locked Loop (PLL) and to a Deserializ-
er that converts NRZI serial data into NRZ parallel characters.
The Framer adjusts the boundaries of these characters to
match those of the original transmitted characters.
Decoder
The parallel characters are passed through a pair of 5B/4B or
6B/5B decoders and returned to their original form. For sys-
tems that make use of external decoding or descrambling, the
decoder may be bypassed.
Receive Data Interface/Receive Data FIFO
Data from the decoder is passed either to a synchronous Re-
ceive FIFO or is passed directly to the output register. The
output register can be configured for either 8-bit character or
10-bit character operation.
When configured for an asynchronous buffered (FIFOed) in-
terface, the data is passed through a 256-character Receive
FIFO that allows data to be read at any rate from DC to 50
14, 17,
35, 55,
62, 64
4,11,
13, 15,
26, 37,
38, 39,
52, 57,
63, 66
V
DD
Power for TTL I/O signals and internal circuits.
V
SS
Ground for TTL I/O signals and internal circuits.
Pin Descriptions
(continued)
Pin
Name
I/O Characteristics
Signal Description
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