參數(shù)資料
型號(hào)： CY7C924ADX
廠商： Cypress Semiconductor Corp.
英文描述： 200 MBaud HOTLink Transceiver(200MBaud HOTLink收發(fā)器)
中文描述： 200 MBd的的HOTLink收發(fā)器（200MBaud的HOTLink收發(fā)器）
文件頁(yè)數(shù)： 8/58頁(yè)
文件大?。?/td> 969K
代理商： CY7C924ADX
CY7C924ADX
Document #: 38-02008 Rev. *E
Page 8 of 58
69
RXEN*
TTL input, sampled
on
RXCLK
↑
,
Internal Pull Up
Receive Enable
. Data enable for the RXDATA[11:0] data bus write and read
operations. Active HIGH when configured for Cascade timing (EXTFIFO is
HIGH), active LOW when configured for UTOPIA timing (EXTFIFO is LOW).
When the Receive FIFO is enabled (FIFOBYP* is HIGH) and RXEN* is
asserted, data is read out of the FIFO on every rising edge of RXCLK. When
RXEN* is deasserted, reads are inhibited and the RXDATA bus is not driven.
When the Receive FIFO is bypassed (FIFOBYP* is LOW) and RXEN* is
asserted, parallel data is clocked out Receive Output Register to the RXData
bus on every RXCLK edge. When RXEN* is deasserted, the RXDATA bus is
not driven.
RXEN* also controls the read and write access to the Serial Address Register.
Receive Clock
. When the Receive FIFO is enabled (FIFOBYP* is HIGH), this
clock is the Receive interface
input
clock and is used to control Receive FIFO
read, reset, and serial register access operations. When the Receive FIFO is
bypassed (FIFOBYP* is LOW), this clock is
output
continuously at the
character rate of the data being received (1/10 or 1/12 of the serial bit rate).
Receive FIFO Full Flag
. Active HIGH when configured for Cascade timing
(EXTFIFO is HIGH), active LOW when configured for UTOPIA timing
(EXTFIFO is LOW). The RXFULL* output is enabled when AM* is asserted,
otherwise it is High-Z.
When the Receive FIFO is addressed (FIFOBYP* is HIGH and the device is
addressed by AM* and selected by RXEN*), RXFULL* is asserted when the
Receive FIFO has room for eight or fewer writes. An RXFULL* condition may
indicate loss of data.
When the Receive FIFO is bypassed (FIFOBYP* is LOW), RXFULL* and
RXHALF* are deasserted to indicate that valid data may be present.
RXFULL* is also used as a BIST progress indicator, and pulses asserted once
every pass through the 511-character BIST loop.
The RXFULL* output is enabled when AM* is asserted, otherwise it is High-Z
Receive FIFO Half-full Flag
. The RXHALF* flag is always active LOW,
regardless of the EXTFIFO* setting.
When the Receive FIFO is enabled (FIFOBYP* is HIGH), this signal is
asserted when the Receive FIFO is half full or more (128 characters). When
the Receive FIFO is bypassed, RXHALF* is deasserted.
RXHALF* is forced to the High-Z state only during a “full-chip” reset (that is,
while RESET*[1:0] are LOW).
8
RXCLK
Bidirectional TTL
clock, Internal Pull-Up
10
RXFULL*
3-state TTL output,
changes following
RXCLK
↑
19
RXHALF*
TTL output, changes
following RXCLK
↑
Pin Descriptions
(continued)
CY7C924ADX HOTLink Transceiver
Pin
Number
Name
I/O Characteristics
Signal Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C924ADX-AC 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C924ADX-ADI 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C924ADX-AI 制造商:Cypress Semiconductor 功能描述:Framer 5V 100-Pin TQFP
CY7C924ADX-AXC 功能描述:網(wǎng)絡(luò)控制器與處理器 IC HOTLink DX COM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CY7C924ADX-AXCKJ 制造商:Cypress Semiconductor 功能描述:
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