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參數(shù)資料
| 型號： | CY7C924ADX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200 MBaud HOTLink Transceiver(200MBaud HOTLink收發(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200MBaud的HOTLink收發(fā)器） |
| 文件頁數(shù)： | 39/58頁 |
| 文件大?。?/td> | 969K |
| 代理商： | CY7C924ADX |
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CY7C924ADX
Document #: 38-02008 Rev. *E
Page 39 of 58
ported across the link. It may also be used to transparently
propagate FIFO flow-control information across the link by
directly connecting the RXHALF* flag of the local receiver to
the TXINT of the local transmitter. The RXINT at the remote
end of the link can then be connected to the TXHALT* input to
halt data transfers at the remote end of the link until the local
Receive FIFO has sufficient room to continue.
Asynchronous Byte-Packed
Asynchronous byte-packed mode contains the same features
as asynchronous decoded, but with support for 10-bit source
data (BYTE8/10* is LOW). The received characters are
decoded first back into 8-bit data characters, which are then
reassembled into 10-bit source data.
Because of the time difference involved with the packing and
unpacking operations, this mode can only be used with the
internal FIFOs enabled.
When receiving extended commands, the larger 10-bit
character size enlarges the extended command space to 1024
(2
10
) possible commands codes.
When receiving a serial address, the larger 10-bit character
size also increases the Serial Address Register to 10 bits. This
allows up to 10 separate domains for multicast addressing or
1024 unique addresses for unicast addressing.
Asynchronous Undecoded
In Asynchronous Undecoded modes, the Receive FIFO is
enabled (FIFOBYP* is HIGH and ENCBYP* is LOW). This
means that all characters received from the serial interface are
written to the Receive FIFO before being passed to the output
register. The Deserializer operates synchronous to the
recovered bit-clock, which is divided by 10 or 12 to generate
the Receive FIFO write clock. Data is read from the Receive
FIFO, using the RXCLK input clock, when addressed by AM*
and selected by RXEN*.
These modes are usually used for products containing
external decoders or descramblers, that must meet specific
protocol requirements. New data may be read from the
Receive FIFO any time that the FIFO status flags indicate a
non-empty condition (RXEMPTY* is deasserted). To ensure
that data is not lost through a FIFO overflow, the Receive FIFO
must be read faster than data is loaded into the Receive FIFO.
If the receiver is to provide framed characters, it is necessary
for the transmit end to include C5.0 (K28.5) characters in the
data stream. This can be done by:
Operating the transmitter in encoded mode and writing C5.0
characters into the data stream
Operating the transmitter in pre-encoded mode and writing
the 10-bit value for an encoded C5.0 character to the data
stream (
1100000101
or
0011111010
)
Deasserting TXEN* when the transmitter is operated in
synchronous mode
Asserting TXHALT*, or by allowing the transmit FIFO to go
empty when it is operated in asynchronous mode.
BIST Operation and Reporting
The CY7C924ADX HOTLink Transceiver incorporates the
same Built-In Self-Test (BIST) capability used with the
HOTLink
CY7B923/
CY7B933
CYP(V)15G0x0x families. This link diagnostic uses a Linear
Feedback Shift Register (LFSR) to generate a 511-character
repeating sequence that is compared, character-for-character,
at the receiver.
BIST mode is intended to check the entire high-speed serial
link at full link-speed, without the use of specialized and
expensive test equipment. The complete sequence of
characters used in BIST are documented in the
HOTLink
Built-In Self-Test
application note.
and
HOTLink
II
BIST Enable Inputs
There are separate BIST enable inputs for the transmit and
receive paths of the CY7C924ADX. These inputs are both
active LOW; i.e., BIST is enabled in its respective section of
the device when the BIST enable input is determined to be at
a logic-0 level. Both BIST enable inputs are asynchronous;
i.e., they are synchronized inside the CY7C924ADX to the
internal state machines.
BIST Transmit Path
The transmit path operation with BIST is controlled by the
TXBISTEN* input and overrides most other inputs (see
Figure 7
). When the Transmit FIFO is enabled (not bypassed)
and TXBISTEN* is recognized internally, all reads from the
Transmit FIFO are suspended and the BIST generator is
enabled to sequence out the 511 character repeating BIST
sequence. If the Transmit Control State Machine was in the
middle of an atomic operation (e.g., sending an extended
command) the Data Character associated with the Special
Character code is transmitted prior to recognition of the
TXBISTEN* signal and suspension of FIFO data processing.
If the recognition occurs in the middle of a data field, the
following data is not transmitted at that time, but remains in the
Transmit FIFO. Once the TXBISTEN* signal is removed, the
data in the Transmit FIFO is again available for transmission.
To ensure proper data handling at the destination, the transmit
host controller should either use TXHALT* or TXSTOP* to
segment transmission of data at specific boundaries, or allow
the Transmit FIFO to completely empty before enabling BIST.
With transmit BIST enabled, the Transmit FIFO remains
available for loading of data. It may be written up to its normal
maximum limit while the BIST operation takes place. To allow
removal of stale data from the Transmit FIFO, it may also be
reset during a BIST operation. The reset operation proceeds
as documented, with the exception of the information
presented on the TXEMPTY* FIFO status flag. Since this flag
is used to present BIST loop status, it continues to reflect the
state of the transmit BIST loop status until TXBISTEN* is no
longer recognized internally. The completion of the reset
operation may still be monitored through the TXFULL* FIFO
status flag.
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| CY7C924DX | 200-MBaud HOTLink Transceiver(200H波特?zé)峤硬迨瞻l(fā)器) |
| CY7C954DX | ATM HOTLink Transceiver(ATM 熱接插收發(fā)器) |
| CY7C964A | Bus Interface Logic Circuit |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C924ADX-AC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C924ADX-ADI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C924ADX-AI | 制造商:Cypress Semiconductor 功能描述:Framer 5V 100-Pin TQFP |
| CY7C924ADX-AXC | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC HOTLink DX COM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CY7C924ADX-AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
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