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參數(shù)資料
| 型號： | CY7C924ADX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 200 MBaud HOTLink Transceiver(200MBaud HOTLink收發(fā)器) |
| 中文描述： | 200 MBd的的HOTLink收發(fā)器（200MBaud的HOTLink收發(fā)器） |
| 文件頁數(shù)： | 18/58頁 |
| 文件大?。?/td> | 969K |
| 代理商： | CY7C924ADX |
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CY7C924ADX
Document #: 38-02008 Rev. *E
Page 18 of 58
the operation mode of the CY7C924ADX as selected by the
SPDSEL and RANGESEL inputs, and to a limited extent, by
the BYTE8/10*, ENCBYP* and FIFOBYP* signals.
Table 4
shows the SPDSEL and RANGESEL for the case where the
FIFOs and encoding are enabled.
Table 5
provides the multi-
plier factors and clocking ranges for various combinations of
signals.
Transmit Control State Machine
The Transmit Control State Machine responds to multiple
inputs to control the data stream passed to the encoder. It
operates in response to:
The state of the FIFOBYP* and LOOPTX inputs
The state of the TXINT input
The presence of data in the Transmit FIFO
The contents of the Transmit FIFO
The contents of the Elasticity Buffer
The state of the transmitter BIST enable (TXBISTEN*)
The state of external halt signals (TXHALT* and TXSTOP*)
These signals are used by the Transmit Control State Machine
to control the data formatter, read access to the Transmit FIFO
and Elasticity Buffer, the Byte-Packer, and BIST. They
determine the content of the characters passed to the Encoder
and Transmit Shifter.
When the Transmit FIFO is bypassed, the Transmit Control
State Machine operates synchronous to REFCLK. In this
mode, data from the TXDATA bus (or other source) passes
directly from the Input Register to the Pipeline Register. If no
data is enabled into the Input register (TXEN* is deasserted)
then the Transmit Control State Machine presents a C5.0
Special Character code to the Encoder to maintain link
synchronization. If both the Encoder and Transmit FIFO are
bypassed and no data is enabled into the Input Register, the
Transmit Control State Machine injects an alternating disparity
sequence of preencoded (10 bit) forms of the C5.0 characters.
This also occurs if the encoder is bypassed, the Transmit FIFO
is enabled, and the Transmit FIFO is empty. However, since
disparity tracking is part of the Encoder, the transmitted C5.0
characters may generate a running disparity error at the
remote receiver. If the attached receiver has its decoder
enabled, these characters may be reported as a normal C5.0,
or as a C1.7 or C2.7 (K28.5 with incorrect running disparity).
Table 4. Speed Select and Range Select Settings, FIFOs
and Encoding enabled
SPDSEL
RANGESEL
Serial
Data Rate
(MBaud)
50–100
50–100
100–200
100–200
REFCLK
Frequency
(MHz)
10–20
20–40
10–20
20–40
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
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| CY7C924DX | 200-MBaud HOTLink Transceiver(200H波特?zé)峤硬迨瞻l(fā)器) |
| CY7C954DX | ATM HOTLink Transceiver(ATM 熱接插收發(fā)器) |
| CY7C964A | Bus Interface Logic Circuit |
| CY7C964A-UM | Bus Interface Logic Circuit |
| CY7C964A-UMB | Bus Interface Logic Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C924ADX-AC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C924ADX-ADI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C924ADX-AI | 制造商:Cypress Semiconductor 功能描述:Framer 5V 100-Pin TQFP |
| CY7C924ADX-AXC | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC HOTLink DX COM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CY7C924ADX-AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
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