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參數(shù)資料
| 型號： | CY7C43684 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進先出帶總線匹配) |
| 中文描述： | 16K的x36 x2雙向同步FIFO瓦特/總線匹配（16K的x36 x2雙向同步先進先出帶總線匹配） |
| 文件頁數(shù)： | 31/37頁 |
| 文件大?。?/td> | 581K |
| 代理商： | CY7C43684 |
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CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
31
PRELIMINARY
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2 regis-
ters matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A
0
–
35
data to the
Mail1 Register when a Port A write is selected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register em-
ploys data lines A
0
–
35
. If the selected Port A bus size is 18 bits,
then the usable width of the Mail1 Register employs data lines
A
0
–
17
. (In this case, A
18
–
35
are
“
don
’
t care
”
inputs.) If the se-
lected Port A bus size is 9 bits, then the usable width of the
Mail1 Register employs data lines A
0
–
8
. (In this case, A
9
–
35
are
“
don
’
t care
”
inputs.)
A LOW-to-HIGH transition on CLKB writes B
0
–
35
data to the
Mail2 Register when a Port B write is selected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register em-
ploys data lines B
0
–
35
. If the selected Port B bus size is 18 bits,
then the usable width of the Mail2 Register employs data lines
B
0
–
17
. (In this case, B
18
–
35
are
“
don
’
t care
”
inputs.) If the se-
lected Port B bus size is 9 bits, then the usable width of the
Mail2 Register employs data lines B
0
–
8
. (In this case, B
9
–
35
are
“
don
’
t care
”
inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-
HIGH transition on CLKB when a Port B read is selected by
CSB, W/RB, and ENB with MBB HIGH. For a 36-bit bus size,
36 bits of mailbox data are placed on B
0
–
35
. For an 18-bit bus
size, 18 bits of mailbox data are placed on B
0
–
17
. (In this case,
B
18
–
35
are indeterminate.) For a 9-bit bus size, 9 bits of mail-
box data are placed on B
0
–
8
. (In this case, B
9
–
35
are indeter-
minate.)
The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH
transition on CLKA when a Port A read is selected by CSA, W/
RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A
0
–
35
. For an 18-bit bus size, 18 bits of mailbox data are placed
on A
0
–
17
. (In this case, A
18
–
35
are indeterminate.) For a 9-bit
bus size, 9 bits of mailbox data are placed on A
0
–
8
. (In this
case, A
9
–
35
are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B bus can be configured in a 36-bit long-word, 18-bit
word, or 9-bit byte format for data read from FIFO1 or written
to FIFO2. The levels applied to the Port B Bus Size Select
(SIZE) and the Bus Match Select (BM) determine the Port B
bus size. These levels should be static throughout FIFO oper-
ation. Both bus size selections are implemented at the com-
pletion of Master Reset, by the time the Full/Input Ready flag
is set HIGH.
Two different methods for sequencing data transfer are avail-
able for Port B when the bus size selection is either byte-or
word-size. They are referred to as Big Endian (most significant
byte first) and Little Endian (least significant byte first). The
level applied to the Big Endian Select (BE) input during the
LOW-to-HIGH transition of MRS1 and MRS2 selects the endi-
an method that will be active during FIFO operation. BE is a
don
’
t care input when the bus size selected for Port B is long
word. The endian method is implemented at the completion of
Master Reset, by the time the Full/Input ready flag is set HIGH.
Only 36-bit long-word data is written to or read from the two
FIFO memories on the CY7C436X4. Bus-matching operations
are done after data is read from the FIFO1 RAM and before
data is written to the FIFO2 RAM. These bus-matching oper-
ations are not available when transferring data via mailbox reg-
isters. Furthermore, both the word- and byte-size bus selec-
tions limit the width of the data bus that can be used for mail
register operations. In this case, only those byte lanes belong-
ing to the selected word- or byte-size bus can carry mailbox
data. The remaining data outputs will be indeterminate. The
remaining data inputs will be
“
don
’
t care
”
inputs. For example,
when a word-size bus is selected, then mailbox data can be
transmitted only between A
0
–
17
and B
0
–
17
. When a byte-size
bus is selected, then mailbox data can be transmitted only be-
tween A
0
–
8
and B
0
–
8
.
Bus-Matching FIFO1 Reads
Data is read from the FIFO1 RAM in 36-bit long-word incre-
ments. If a long-word bus size is implemented, the entire long-
word immediately shifts to the FIFO1 output register. If byte or
word size is implemented on Port B, only the first one or two
bytes appear on the selected portion of the FIFO1 output reg-
ister, with the rest of the long-word stored in auxiliary registers.
In this case, subsequent FIFO1 reads output the rest of the
long-word to the FIFO1 output register.
When reading data from FIFO1 in the byte or word format, the
unused B
0
–
35
outputs are indeterminate.
Bus-Matching FIFO2 Writes
Data is written to the FIFO2 RAM in 36-bit long-word incre-
ments. Data written to FIFO2 with a byte or word bus size
stores the initial bytes or words in auxiliary registers. The
CLKB rising edge that writes the fourth byte or the second
word of the long-word to FIFO2 also stores the entire long-
word in FIFO2 RAM.
When reading data from FIFO2 in byte or word format, the
unused B
0
–
35
outputs are LOW.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at least one word has been read since the last reset
cycle. A LOW pulse on RT1, RT2 resets the internal read point-
er to the first physical location of the FIFO. CLKA and CLKB
may be free running but must be disabled during and t
RTR
after
the retransmit pulse. With every valid read cycle after retrans-
mit, previously accessed data is read and the read pointer is
incremented until it is equal to the write pointer. Flags are gov-
erned by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to the
FIFO after activation of RT1, RT2 are transmitted also. The full
depth of the FIFO can be repeatedly retransmitted.
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|---|---|
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